74LVC1G80 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC1G80 Datasheet PDF : 16 Pages
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NXP Semiconductors
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
74LVC1G80
Single D-type flip-flop; positive-edge trigger
VI
D input
GND
VI
CP input
GND
VOH
Q output
VOL
VM
t PLH
VM
VM
t PHL
VM
mna652
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
Fig 7. Clock (CP) to output (Q) propagation delay times
VI
D input
GND
VI
CP input
GND
VOH
Q output
VOL
VM
th
t su(L)
1/ fmax
VM
tW
t PLH
VM
th
t su(H)
t PHL
mna653
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 8. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold
times and maximum clock pulse frequency
74LVC1G80_8
Product data sheet
Rev. 08 — 29 August 2007
© NXP B.V. 2007. All rights reserved.
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