74LVC3G07 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC3G07 Datasheet PDF : 21 Pages
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NXP Semiconductors
5. Functional diagram
74LVC3G07
Triple buffer with open-drain output
1A
1Y
2A
2Y
1
1A
1Y
1
2A
2Y
3A
3Y
001aah762
Fig 1. Logic symbol
1
3A
3Y
001aah763
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
Y
A
GND mna591
Fig 3. Logic diagram (one driver)
74LVC3G07
1A 1
3Y 2
2A 3
GND 4
8 VCC
7 1Y
6 3A
5 2Y
001aab022
Fig 4. Pin configuration SOT505-2 and SOT765-1
74LVC3G07
1A 1
8 VCC
3Y 2
7 1Y
2A 3
6 3A
GND 4
5 2Y
001aac022
Transparent top view
Fig 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC3G07
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 9 April 2013
© NXP B.V. 2013. All rights reserved.
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