N28F020 데이터 시트보기 (PDF) - Intel

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N28F020

2048K (256K x 8) CMOS FLASH MEMORY

Intel 

28F020

Symbol

A0 – A17

DQ0 – DQ7

CE

OE

WE

VPP

VCC

VSS

Type

INPUT

INPUT OUTPUT

INPUT

INPUT

INPUT

Figure 1 28F020 Block Diagram

290245 – 1

Table 1 Pin Description

Name and Function

ADDRESS INPUTS for memory addresses Addresses are internally

latched during a write cycle

DATA INPUT OUTPUT Inputs data during memory write cycles

outputs data during memory read cycles The data pins are active high

and float to tri-state OFF when the chip is deselected or the outputs

are disabled Data is internally latched during a write cycle

CHIP ENABLE Activates the device’s control logic input buffers

decoders and sense amplifiers CE is active low CE high

deselects the memory device and reduces power consumption to

standby levels

OUTPUT ENABLE Gates the devices output through the data buffers

during a read cycle OE is active low

WRITE ENABLE Controls writes to the control register and the array

Write enable is active low Addresses are latched on the falling edge

and data is latched on the rising edge of the WE pulse

Note With VPP s 6 5V memory contents cannot be altered

ERASE PROGRAM POWER SUPPLY for writing the command

register erasing the entire array or programming bytes in the array

DEVICE POWER SUPPLY (5V g10%)

GROUND

2

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