N28F020 데이터 시트보기 (PDF) - Intel

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N28F020

2048K (256K x 8) CMOS FLASH MEMORY

Intel 

28F020

Table 2 28F020 Bus Operations

Mode

VPP(1) A0 A9 CE

Read

VPPL A0 A9 VIL

Output Disable

VPPL X

X

VIL

READ-ONLY Standby

VPPL X

X

VIH

Intelligent Identifier (Mfr)(2)

VPPL VIL VID(3) VIL

Intelligent Identifier (Device)(2) VPPL VIH VID(3) VIL

Read

VPPH A0 A9 VIL

READ WRITE Output Disable

Standby(5)

VPPH X

X

VIL

VPPH X

X

VIH

Write

VPPH A0 A9 VIL

OE

VIL

VIH

X

VIL

VIL

VIL

VIH

X

VIH

WE

VIH

VIH

X

VIH

VIH

VIH

VIH

X

VIL

DQ0 – DQ7

Data Out

Tri-State

Tri-State

Data e 89H

Data e BDH

Data Out(4)

Tri-State

Tri-State

Data In(6)

NOTES

1 Refer to DC Characteristics When VPP e VPPL memory contents can be read but not written or erased

2 Manufacturer and device codes may also be accessed via a command register write sequence Refer to Table 3 All

other addresses low

3 VID is the Intelligent Identifier high voltage Refer to DC Characteristics

4 Read operations with VPP e VPPH may access array data or the Intelligent Identifier codes

5 With VPP at high voltage the standby current equals ICC a IPP (standby)

6 Refer to Table 3 for valid Data-In during a write operation

7 X can be VIL or VIH

Or the system designer may choose to ‘‘hardwire’’

VPP making the high voltage supply constantly

available In this case all Command Register func-

tions are inhibited whenever VCC is below the write

lockout voltage VLKO (See Power Up Down Protec-

tion ) The 28F020 is designed to accommodate ei-

ther design practice and to encourage optimization

of the processor-memory interface

The two step program erase write sequence to the

Command Register provides additional software

write protection

When VPP is high (VPPH) the read operation can be

used to access array data to output the Intelligent

Identifier codes and to access data for program

erase verification When VPP is low (VPPL) the read

operation can only access the array data

Output Disable

With OE at a logic-high level (VIH) output from the

device is disabled Output pins are placed in a high-

impedance state

BUS OPERATIONS

Read

The 28F020 has two control functions both of which

must be logically active to obtain data at the out-

puts Chip-Enable (CE ) is the power control and

should be used for device selection Output-Enable

(OE ) is the output control and should be used

to gate data from the output pins independent of

device selection Refer to AC read timing

waveforms

Standby

With CE at a logic-high level the standby opera-

tion disables most of the 28F020’s circuitry and sub-

stantially reduces device power consumption The

outputs are placed in a high-impedance state inde-

pendent of the OE signal If the 28F020 is dese-

lected during erasure programming or program

erase verification the device draws active current

until the operation is terminated

7

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