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74LVX574MTR

LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP (3-STATE NON INV.) WITH 5V TOLERANT INPUTS

STMicroelectronics 

74LVX574

LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP

(3-STATE NON INV.) WITH 5V TOLERANT INPUTS

s HIGH SPEED:

fMAX = 125MHz (TYP.) at VCC = 3.3V

s 5V TOLERANT INPUTS

s POWER-DOWN PROTECTION ON INPUTS

s INPUT VOLTAGE LEVEL:

VIL = 0.8V, VIH = 2V at VCC =3V

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s LOW NOISE:

VOLP = 0.3V (TYP.) at VCC =3.3V

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 4 mA (MIN) at VCC =3V

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 574

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVX574 is a low voltage CMOS OCTAL

D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C2MOS

technology. It is ideal for low power, battery

operated and low noise 3.3V applications.

This 8 bit D-Type flip-flop is controlled by a clock

input (CK) and an output enable input (OE). On

the positive transition of the clock, the Q outputs

will be set to the logic state that were setup at the

PIN CONNECTION AND IEC LOGIC SYMBOLS

SOP

TSSOP

ORDER CODES

PACKAGE

SOP

TSSOP

TUBE

74LVX574M

T&R

74LVX574MTR

74LVX574TTR

D inputs. While the (OE) input is low, the 8 outputs

will be in a normal logic state (high or low logic

level) and while high level the outputs will be in a

high impedance state. The output control does not

affect the internal operation of flip flops; that is,

the old data can be retained or the new data can

be entered even while the outputs are off.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

This device can be used to interface 5V to 3V. It

combines high speed performance with the true

CMOS low power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

July 2001

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