74VCX16841(1999) 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74VCX16841
(Rev.:1999)
(Rev.:1999)
Fairchild Semiconductor
74VCX16841 Datasheet PDF : 7 Pages
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Connection Diagram
Truth Tables
Inputs
Outputs
LE1
OE1
D0–D9
O0–O9
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
Inputs
Outputs
LE2
OE2
D10–D19 O10–O19
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW of Latch Enable
Functional Description
The 74VCX16841 contains twenty D-type latches with 3-
STATE outputs. The device is byte controlled with each
byte functioning identically, but independent of the other.
Control pins can be shorted together to obtain full 20-bit
operation. The following description applies to each byte.
When the Latch Enable (LEn) input is HIGH, data on the Dn
enters the latches. In this condition the latches are trans-
parent, i.e., a latch output will change states each time its
Logic Diagram
D-type input changes. When LEn is LOW, the latches store
information that was present on the D-type inputs a setup
time preceding the HIGH-to-LOW transition on LEn. The 3-
STATE outputs are controlled by the Output Enable (OEn)
input. When OEn is LOW the standard outputs are in the 2-
state mode. When OEn is HIGH, the standard outputs are
in the high impedance mode but this does not interfere with
entering new data into the latches.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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