78P2351R 데이터 시트보기 (PDF) - Teridian Semiconductor Corporation

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78P2351R

Serial 155M NRZ to CMI Converter

Teridian Semiconductor Corporation 

78P2351R

Serial 155M

NRZ to CMI Converter

REGISTER DESCRIPTION (continued)

ADDRESS 1-1: SIGNAL CONTROL REGISTER

BIT

NAME

TYPE

DFLT

VALUE

DESCRIPTION

Transmit CMI Inversion:

7 TCMIINV R/W

This bit will flip the polarity of the transmit CMI data outputs at CMIP/N.

0 For debug use only.

0: Normal

1: Invert

Receive CMI Inversion:

6 RCMIINV R/W

This bit will flip the polarity of the receive CMI data inputs at RXP/N. For

0 debug use only.

0: Normal

1: Invert

Receive Loss of Signal Override/Disable:

5 LOSOR R/W

When set, the LOS signal will always remain low.

0

0: Normal

1: Forces LOS output to be low and resets counter

Analog Loopback Selection:

4 RLBK R/W

0

RLBK LLBK

0

0 Normal operation

1

0 Remote Loopback Enable: Recovered receive data

is looped back to the transmit driver for retransmission.

3 LLBK R/W

0

0

1 Local Loopback Enable: The transmit data is

looped back and used as the input to the receiver.

2:1

--

R/W

00 Reserved.

0 FRST R/W

FIFO Reset:

0: Normal operation

1: Reset FIFO pointers to default locations.

0

This reset should be initiated anytime the transmitter or IC powers up to

ensure the FIFO is centered after internal VCO clocks and external

transmit clocks are stable.

NOTE: FIFO reset not required for Plesiochronous Mode

ADDRESS 1-2: ADVANCED TRANSMIT CONTROL REGISTER 1

BIT

NAME

TYPE

DFLT

VALUE

DESCRIPTION

7:1

--

R/W

000000

0

Reserved.

Transmit Fixed Equalizer Enable:

0 TXEQ R/W

When enabled, compensates for between 0.75m and 1.5m of FR4 trace

0 to the LVPECL data inputs SIDP/N

0: Normal Operation

1: Enable equalizer

Page: 11 of 31

2006 Teridian Semiconductor Corporation

Rev. 2.1

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