A3950 데이터 시트보기 (PDF) - Allegro MicroSystems
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A3950 Datasheet PDF : 9 Pages
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Preliminary Data Sheet
Subject to Change without Notice
November 4, 2005
A3950
DMOS Full-Bridge Motor Driver
Timing Diagram: PWM Control
SLEEP
ENABLE
PHASE
MODE
VBB
VOUTA
0
VBB
VOUTB
0
IOUTX 0
A3950DS
A
1
2
VBB
15
OutA
3
24
OutB
3
4
5
OutA
A Charge pump and VREG power-on delay (≈200 µs)
6
7
8
9
VBB
6
7
OutB
8
9
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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