A3949(2013) 데이터 시트보기 (PDF) - Allegro MicroSystems
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A3949 Datasheet PDF : 7 Pages
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A3949
DMOS Full-Bridge Motor Driver
PWM Control Timing Diagram
SLEEP
ENABLE
PHASE
MODE
VBB
OUTA
0V
VBB
OUTB
0V
IOUT
0A
A
VBB
1
2
3
4
5
6
7
8
9
VBB
OUTA
1
5
3
2
4
OUTB
OUTA
6
7
9
8
OUTB
A Charge pump and VREG power-up delay (approximately 200 us)
Allegro MicroSystems, LLC
4
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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