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A4979 데이터 시트보기 (PDF) - Allegro MicroSystems

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A4979 Datasheet PDF : 44 Pages
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A4979
Microstepping Programmable Stepper Motor Driver
With Stall Detect and Short Circuit Protection
For example:
• if RS = 180 mΩ and VREF = 2 V, then ISMAX = 694 mA
• if MXI1= 1 and MXI0 = 0, then IPMAX = 520 mA
The actual current delivered to each phase at each Step Angle
Number is determined by the value of IPMAX and the contents
of the Phase Current table. For each phase, the value in the table
is passed to the DAC, which uses IPMAX as the reference 100%
level (code 63) and reduces the current target depending on the
DAC code. The output from the DAC is used as the input to the
current comparators.
The current comparison is ignored at the start of the PWM
on-time for a duration referred to as the blank time. The blank
time is necessary to prevent any capacitive switching currents
from causing a peak current detection.
The PWM on-time starts at the beginning of each PWM period.
The current rises in the phase winding until the sense voltage
reaches the required current level. At this point the PWM off-time
starts and the bridge is switched into one of two decay modes,
slow decay or fast decay:
• Slow decay is most effective when the current is rising from
step to step, and it occurs when the phase winding is effectively
shorted by switching-on either both high-side FETs or both low-
side FETs in the full bridge.
• Fast decay is most effective when the current is falling from
step to step, and it occurs when the voltage on the phase is
reversed.
One disadvantage of fast decay is the increased current ripple in
the phase winding. However, this can be reduced while main-
taining good current control, by using a short time of fast decay
followed by slow decay for the remainder of the PWM off-time.
This technique is commonly referred to as mixed decay
The A4979 provides two methods to determine the PWM
frequency: fixed off-time and fixed frequency. At power-up the
default mode is fixed off-time. Fixed frequency can be selected
through the serial interface. Fixed off-time provides a marginal
improvement in current accuracy over a wide range of current
levels. Fixed frequency provides a fixed fundamental frequency
to allow more precise supply filtering for EMC reduction. In both
cases the PWM off-time will not be present if the peak current
limit is not attained during the PWM on-time.
Phase Current Table
The relative phase currents are defined by the Phase Current table
(table 7). This table contains 64 lines and is addressed by the Step
Angle Number, where Step Angle Number 0 corresponds to 0° or
360°. The Step Angle Number is generated internally by the step
sequencer, which is controlled either by the STEP and DIR inputs
or by the step change value from the serial input. The Step Angle
Number determines the motor position within the 360° electri-
cal cycle and a sequence of Step Angle Numbers determines the
motor movement. Note that there are four full mechanical steps
per 360° electrical cycle.
Each line of the Phase Current table (table 7) has a 6-bit value per
phase to set the DAC level for that phase, plus an additional bit
per phase to determine the current direction for that phase. The
Step Angle Number sets the electrical angle of the stepper motor
in one-sixteenth microsteps, approximately equivalent to electri-
cal steps of 5.625°.
On first power-up or after a VDD power-on reset, the Phase Cur-
rent table values are reset to define a sinusoidal current profile
and the Step Angle Number is set to 8, equivalent to the electri-
cal cycle 45° position. This position is defined as the “home”
position. The maximum current in each phase, IPMAX , is defined
by the sense resistor and the Maximum Current setting (bits
MXI[0:1]) in Configuration Register 0. The phase currents for
each entry in the Phase Current table are expressed as a percent-
age of this maximum phase current.
When using the STEP and DIR inputs to control the stepper
motor, the A4979 automatically increases or decreases the Step
Angle Number according to the step sequence associated with
the selected step mode. The default step mode, reset at power-
up or after a power on reset, is full step. Half-, quarter-, and
sixteenth-step sequences are also available when using the STEP
and DIR inputs, and are selected using the logical OR of the MS0
and MS1 inputs and the MS0 and MS1 bits in Configuration Reg-
ister 0. The eighth-step sequence is shown in the Phase Current
table for reference only.
Allegro MicroSystems, LLC
11
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com

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