AAT1157 데이터 시트보기 (PDF) - Analog Technology Inc

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AAT1157

1MHz 1.2A Buck DC/DC Converter

Analog Technology Inc 

AAT1157

1MHz 1.2A Buck DC/DC Converter

Output Capacitor

Since there are no external compensation compo-

nents, the output capacitor has a strong effect on loop

stability. Larger output capacitance reduces the

crossover frequency while increasing the phase mar-

gin. For the 2.5V 1.2A design using the 3.0µH induc-

tor, a 40µF capacitor provides a stable output. Table 1

provides a list of suggested output capacitor values

for various output voltages. In addition to assisting in

stability, the output capacitor limits the output ripple

and provides holdup during large load transitions. The

output capacitor RMS ripple current is given by:

1

IRMS

=

2

⋅

⋅ VOUT ⋅ (VIN - VOUT)

3

L ⋅ F ⋅ VIN

For an X7R or X5R ceramic capacitor, the ESR is

very low and the dissipation due to the RMS current

of the capacitor is not a concern. Tantalum capaci-

tors with sufficiently low ESR to meet output voltage

ripple requirements also have an RMS current rating

well beyond that actually seen in this application.

Layout

Figures 2 and 3 display the suggested PCB layout

for the AAT1157. The following guidelines should

be used to help insure a proper layout.

1. The input capacitor (C1) should connect as

closely as possible to VP (Pins 10, 11, and 12)

and PGND (Pins 1, 2, and 3).

2. C3-C4 and L1 should be connected as close-

ly as possible. The connection from L1 to the

LX node should be as short as possible.

3. The trace connecting the FB pin to resistors R3

and R4 should be as short as possible by plac-

ing R3 and R4 immediately next to the

AAT1157. The sense trace connection R3 to

the output voltage should be separate from any

power trace and connect as closely as possible

to the load point. Sensing along a high-current

load trace will degrade DC load regulation.

4. The resistance of the trace from the load return to

the PGND (Pins 1, 2, and 3) and SGND (Pin 5)

should be kept to a minimum. This will help to

minimize any error in DC regulation due to differ-

ences in the potential of the internal signal

ground and the power ground. SGND (Pin 5) can

also be used to remotely sense the output

ground at the point of load to improve regulation.

5. A low pass filter (R1 and C2) provides a clean-

er bias source for the AAT1157 active circuitry.

C2 should be placed as closely as possible to

SGND (Pin 5) and VCC (Pin 9).

6. For good heat transfer, four 15 mil vias spaced

on a 26 mil grid connect the QFN central pad-

dle to the bottom side ground plane, as shown

in Figures 2 and 3.

Thermal Calculations

There are three types of losses associated with the

AAT1157: MOSFET switching losses, conduction

losses, and quiescent current losses. The conduc-

tion losses are due to the RDSON characteristics of

the internal P- and N-channel MOSFET power

devices. At full load, assuming continuous conduc-

tion mode (CCM), a simplified form of the total loss-

es is given by:

Figure 2: Evaluation Board Top Side.

1157.2005.11.1.4

Figure 3: Evaluation Board Bottom Side.

9

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