AAT3194 데이터 시트보기 (PDF) - Advanced Analogic Technologies

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AAT3194

High Efficiency 1.5X Fractional Charge Pump For White LED Applications

Advanced Analogic Technologies 

PRODUCT DATASHEET

AAT3194

ChargePumpTM High Efficiency 1.5X Fractional Charge Pump For White LED Applications

Functional Block Diagram

IN

Soft Start

600kHz

Oscillator

Voltage

Reference

1.5X

Charge

Pump

C1+

C1-

C2+

C2-

OUT

D1

EN/SET

S2Cwire

Interface

5

32x8 bit

ROM

8

Current

Mode

DAC

D2

D3

D4

GND

Functional Description

The AAT3194 is a high efficiency 1.5X fractional charge

pumps intended for white LED backlight applications. The

fractional charge pump consists of a linear regulator fol-

lowed by a 1.5X charge pump. The AAT3194 requires only

four external components: two 1µF ceramic capacitors for

the charge pump flying capacitors (C1 and C2), one 1µF

ceramic capacitor for CIN, and one 0.33µF to 1µF ceramic

capacitor for COUT. The charge pump output is converted

into four constant current outputs (D1 to D4) to drive four

individual LEDs with a maximum of 20mA each. The cur-

rent source output magnitude is controlled by the EN/SET

serial data S2Cwire interface. The interface records rising

edges of the EN/SET pin and decodes them into 32 indi-

vidual current level settings each 1dB apart (see Table 1,

Current Level Settings). Code 32 is full scale, and Code 1

is full scale attenuated by 31dB. The modulo 32 interface

wraps states back to state 1 after the 32nd clock. With

each EN/SET pulse, the output current increases by 1dB.

To decrease the output current by 1dB, 31 EN/SET clock

pulses are required. The counter can be clocked at speeds

up to 1MHz, so intermediate states are not visible. The

first rising edge of EN/SET enables the IC and initially sets

the output LED current to -31dB, the lowest setting equal

to 525µA. Once the final clock cycle is input for the

desired brightness level, the EN/SET pin is held high to

maintain the device output current at the programmed

level. The device is disabled 500µs after the EN/SET pin

transitions to a logic low state.

8

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3194.2008.05.1.1

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