ACE9030M 데이터 시트보기 (PDF) - Mitel Networks

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ACE9030M

Radio Interface and Twin Synthesiser

Mitel Networks 

ACE9030

AMPP1

AMPN1

AMPP2

AMPN2

ADC1

ADC2A

ADC2B

ADC3A

ADC3B

ADC4

ADC5

AFCIN

C8B

CLK8

LO2

CIN2

CIN1

LATCHB

VDDSUB2

VDDSUB

DECOUP

VDDSA

VSSSA

FIM

FIMB

CL

DATA

LATCHC

TEST

FIA

FIAB

+

−

LEVEL SENSE

+

−

ADC1

VDDL

VSSL

OSC8

PLL.

MULT

x3, x5

CRYSTAL

OSC.

DEFINE

LEVELS

DEMOD

VREF

+

−

MIXER

DATA &

XO

CONTROL

SERIAL BUS I/O TO

RADIO INTERFACE

FILTER

DAC1

DAC2

DAC3

BAND-GAP

REFERENCE

BIAS

GEN.

MAIN SYNTHESISER

with FRACTIONAL-N

TEST

SEL.

REFERENCE

DIVIDER

LOCK

DETECT

AUXILIARY

SYNTHESISER

RXCD

VDDX

DOUT0

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

AUDIO

BP

AFCOUT

DAC1

DAC2

DAC3

RSC

RSMA

PDP

PDI

MODMP

MODMN

VDDD

VSSD

PDA

Fig.3 ACE9030 Block diagram

2

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