ACPL-38JT-000E 데이터 시트보기 (PDF) - Avago Technologies
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ACPL-38JT-000E Datasheet PDF : 33 Pages
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Notes:
1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation
Characteristics Table.
3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 12 shorted together.
4. In order to achieve the absolute maximum power dissipation specified, pins 1, 9, and 12 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require de-rating.
5. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO
peak minimum = 2.0 A. See Applications section for additional details on IOH peak. De-rate linearly from 3.0 A at +25°C to 2.5 A at +125°C. This
compensates for increased IOPEAK due to changes in VOL over temperature.
6. This supply is optional. Required only when negative gate drive is implemented.
7. Maximum pulse width = 50 s, maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
9. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero units.
10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
11. Once VOUT of the ACPL-38JT is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the ACPL-38JT will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the
DESAT detection and UVLO features of the ACPL-38JT work in conjunction to ensure constant IGBT protection.
12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details.
13. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE.
14. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE.
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
17. As measured from VIN+, VIN- to VOUT.
18. The difference between tPHL and tPLH between any two ACPL-38JT parts under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low.
22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 μs is the guaranteed
minimum FAULT signal pulse width when the ACPL-38JT is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the
end of this data sheet for further details.
23. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3K pull-up resistor is needed in fault detection mode.
24. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
25. Does not include LED2 current during fault or blanking capacitor discharge current.
26. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 A
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
27. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE.
28. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the
IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper operating
voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
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