ACPL-796J-060E 데이터 시트보기 (PDF) - Avago Technologies
부품명
상세내역
제조사
ACPL-796J-060E Datasheet PDF : 16 Pages
| |||
Latch-up Consideration
Latch-up risk of CMOS devices needs careful consider-
ation, especially in applications with direct connection to
signal source that is subject to frequent transient noise.
The analog input structure of the ACPL-796J is designed
to be resilient to transients and surges, which are often
encountered in highly noisy application environments
such as motor drive and other power inverter systems.
Other situations could cause transient voltages to the
inputs include short circuit and overload conditions. The
ACPL-796J is tested with DC voltage of up to –2 V and 2-
second transient voltage of up to –6 V to the analog inputs
and there is no latch-up or damage to the device.
Modulator Data Output
Input signal information is contained in the modulator
output data stream, represented by the density of ones
and zeros. The density of ones is proportional to the input
signal voltage, as shown in Figure 15. A differential input
signal of 0 V ideally produces a data stream of ones 50%
of the time and zeros 50% of the time. A differential input
of –200 mV corresponds to 18.75% density of ones, and
a differential input of +200 mV is represented by 81.25%
density of ones in the data stream. A differential input of
+320 mV or higher results in ideally all ones in the data
stream, while input of –320 mV or lower will result in all
zeros ideally. Table 10 shows this relationship.
MODULATOR OUTPUT
ANALOG INPUT
Figure 15. Moudlator output vs. analog input.
+FS (ANALOG INPUT)
0 V (ANALOG INPUT)
–FS (ANALOG INPUT)
TIME
Table 10. Input voltage with ideal corresponding density of 1s at modulator data output, and ADC code.
Analog Input
Full-Scale Range
+Full-Scale
+Recommended Input Range
Zero
–Recommended Input Range
Voltage Input
640 mV
+320 mV
+200 mV
0 mV
–200 mV
Density of 1s
100%
81.25%
50%
18.75%
ADC Code (16-bit unsigned decimation)
65,535
53,248
32,768
12,288
–Full-Scale
–320 mV
0%
0
Notes:
1. With bipolar offset binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until
the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
2. Ideal density of 1s at modulator data output can be calculated with VIN/640 mV + 50%; similarly, the ADC code can be calculated with (VIN/640 mV)
× 65,536 + 32,768, assuming a 16-bit unsigned decimation filter.
11
Share Link: 