ACPL-K34T-500E 데이터 시트보기 (PDF) - Avago Technologies
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ACPL-K34T-500E
Avago Technologies
ACPL-K34T-500E Datasheet PDF : 15 Pages
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Application Information
Typical High Speed MOSFET Gate Drive Circuit
+5V
VDD
0.1uF
U5
PHA
uP
PHA
U6
Anti-cross conduction drive logic
U1
Rin1 AN VCC
Rin2 NC
V OUT
CA
NC
NC
VEE
10u
4.7Ω
ACPL-K34T
+12V
10V
10uF
D1
PHA
PHA
LED(U1)
LED(U2)
Rin3
Rin4
Figure 16. Typical high-speed MOSFET gate drive circuit
U2
AN VCC
NC
V OUT
CA
NC
NC
VEE
ACPL-K34T
10u
4.7Ω
U3
AN VCC
Q1 NC
V OUT
CA
NC
NC
VEE
ACPL-K34T
U4
AN VCC
Q2 NC
V OUT
CA
NC
NC
VEE
ACPL-K34T
10u
4.7Ω
+HVDC
Q3
D2
10u
4.7Ω
Q4
- HVDC
Anti-Cross Conduction Drive
One of the many benefits of using ACPL-K34T is the ease to implement anti-cross conduction drive between the high
side and low side gate drivers to prevent shoot through event. This safety interlock drive can be realized by interlock-
ing the output of buffer U5 and U6 to both high and low side gate drivers, as shown in Figure 16. However, due to the
propagation delay difference between optocouplers, certain amount of dead time has to be added to ensure sufficient
dead time at MOSFET gate. Refer to Dead Time and Propagation Delay section for more details.
Recommended LED Drive Circuits
Common mode noise exists whenever there is a difference in the ground level of the optocoupler’s input control cir-
cuitry and output control circuitry. Figure 17 and 18 show recommended LED drive circuits for high common mode
rejection (CMR) performance of the optocoupler gate driver. Split limiting resistors are used to balance the impedance
at both anode and cathode of the input LED for high common mode noise rejection (see Figure 15).
Open drain and open collector drive circuits showed in Figure 19 are not recommended. During the off state of the MOS-
FET/transistor, cathode of the input LED sees high impedance and becomes sensitive to noise. In any cases, if designer
still prefers to use single MOSFET/transistor drive over the recommended CMOS buffer drive showed in Figure 17 and
18, designer can choose alternative circuits showed in Figure 20; however M1/Q1 in Figure 20 drive circuits will shunt
current during LED off state, which result in more power consumption.
Drive Power
If CMOS buffer is used to drive LED, it is recommended to connect the CMOS buffer at the LED cathode. This is because
the sinking capability of the NMOS is usually more than the driving capability of the PMOS in a CMOS buffer.
Drive Logic
Designer can configure LED drive circuits for non-inverting and inverting logic as recommended in Figure 17 and 18.
External power supply, VDD1 has to be connected to the CMOS buffer for the inverting and non-inverting logic to work.
If VDD1 supply is lost, LED will be permanently off and output will be at low.
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