ACPL-M61L-560E 데이터 시트보기 (PDF) - Avago Technologies
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ACPL-M61L-560E Datasheet PDF : 16 Pages
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Switching Specifications (AC)
Over the recommended temperature (TA = –40°C to +105°C) and supply voltage (2.7 V ≤ VDD ≤ 5.5 V). All typical speci-
fications are at VDD = 5 V, TA = 25°C.
Parameter
Symbol
Min
Typ
Max Units
Test Conditions
Propagation Delay Time
tPHL
to Logic Low Output [1]
46
80 ns
IF = 2 mA, VI = 5 V, RT = 1.68 kΩ,
CL = 15 pF, CMOS Signal Levels.
Propagation Delay Time
to Logic High Output [1]
Pulse Width
Pulse Width Distortion[2]
Propagation Delay Skew [3]
tPLH
tPW
PWD
tPSK
40
80 ns
100
ns
6
30 ns
30 ns
IF = 2 mA, VI = 3.3 V, RT = 870 Ω,
CL = 15 pF, CMOS Signal Levels.
Figure 6,7
Output Rise Time
tR
(10% – 90%)
12
ns
IF = 2 mA, VI = 5 V, RT = 1.68 kΩ,
CL = 15 pF, CMOS Signal Levels.
10
ns
IF = 2 mA, VI = 3.3 V, RT = 870 Ω,
CL = 15 pF, CMOS Signal Levels.
Output Fall Time
tF
(90% - 10%)
12
ns
IF = 2 mA, VI = 5 V, RT = 1.68 kΩ,
CL = 15 pF, CMOS Signal Levels.
10
ns
IF = 2 mA, VI = 3.3 V, RT = 870 Ω,
CL = 15 pF, CMOS Signal Levels.
Static Common Mode
Transient Immunity at
Logic High Output [4]
| CMH |
20
35
kV/µs
VCM = 1000 V, TA = 25°C, IF = 0 mA,
VI = 0 V (RT =1.68 kΩ) or (RT = 870Ω),
CL = 15 pF, CMOS Signal Levels.
Figure 8
Static Common Mode
Transient Immunity at
Logic Low Output [5]
| CML |
20
35
kV/µs
VCM = 1000 V, TA = 25°C, VI = 5 V
(RT = 1.68 kΩ) or VI = 3.3 V
(RT = 870Ω), IF = 2 mA, CL= 15 pF,
CMOS Signal Levels.
Figure 8
Dynamic Common Mode
Transient Immunity [6]
CMRD
35
kV/µs
VCM = 1000 V, TA = 25°C, IF = 2 mA,
VI = 5 V (RT = 1.68 kΩ) or VI = 3.3 V
(RT = 870Ω), 10MBd datarate,
the absolute increase of PWD < 10ns
Figure 8
Notes:
1. tPHL propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% VDD of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% level of the rising edge of the VO
signal.
2. PWD is defined as |tPHL - tPLH|.
3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
6. CMD is the maximum tolerable rate of the common mode voltage during data transmission to assure that the absolute increase of the PWD is less
than 10 ns.
Package Characteristics
All typicals are at TA = 25°C.
Parameter
Symbol Part Number Min
Typ
Max
Input-Output Insulation
VISO
ACPL-064L
3750
ACPL-M61L
Input-Output Resistance
RI-O
Input-Output Capacitance CI-O
ACPL-W61L
ACPL-K64L
5000
1012
0.6
Units Test Conditions
Vrms
RH < 50% for 1 min.
TA = 25°C
Ω
VI-O = 500 V
pF
f = 1 MHz, TA = 25°C
8
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