ACPL-W480-000E 데이터 시트보기 (PDF) - Avago Technologies
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ACPL-W480-000E
Avago Technologies
ACPL-W480-000E Datasheet PDF : 10 Pages
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Table 6. Switching Specifications
Over recommended operating conditions TA = -40 °C to 100 °C, VCC = +4.5 V to 20 V, IF(ON) = 6 mA to 10 mA, VF(OFF) = 0
V to 0.8 V, unless otherwise specified. All typicals at TA = 25 °C.
Parameter
Symbol
Min. Typ. Max. Units Test Conditions
Fig. Note
Propagation Delay Time to
tPHL
Logic Low Output Level
150 350
ns
With Peaking
Capacitor
5, 6 1
Propagation Delay Time to
tPLH
Logic High Output Level
110 350
ns
With Peaking
Capacitor
5, 6 1
Pulse Width Distortion
|tPHL - tPLH|
250
ns
2
= PWD
Propagation Delay Difference PDD
-100
250
ns
3
Between Any 2 Parts
Output Rise Time (10-90%)
tr
16
ns
5, 8
Output Fall Time (90-10%)
tf
20
ns
5, 8
Logic High Common Mode
|CMH|
20
Transient Immunity
kV/µs |VCM| = 1000 V, IF = 6.0 11 4
mA, VCC = 5 V, TA = 25˚C
Logic Low Common Mode
|CML|
20
Transient Immunity
kV/µs |VCM| = 1000 V, VF = 0 V, 11 4
VCC = 5 V, TA = 25˚C
Table 7. Package Characteristics
Parameter
Input-Output Momentary
Withstand Voltage*
Input-Output Resistance
Input-Output Capacitance
Symbol
VISO
RI-O
CI-O
Min. Typ. Max. Units Test Conditions
Fig. Note
3750**
5000***
Vrms RH < 50%, t = 1 min.
5, 6
TA = 25°C
1012
VI-O = 500 Vdc
5
0.6
f = 1 MHz, VI-O = 0 Vdc
5
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable).
** For all ACPL-P480 devices except Option 020
*** For ACPL-W480 and Option 020 of ACPL-P480)
Notes:
1. The tPLH propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The tPHL propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing
edge of the output pulse.
2. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH | for any given device.
3. The difference between tPLH and tPHL between any two devices under the same test condition.
4. CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, VO > 2.0 V.
CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, VO < 0.8 V.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for one second (leakage
detection current limit, II-O ≤ 5 µA). ; each optocoupler with option 020 is proof tested by applying an insulation test voltage ≥ 6000 VRMS for
1 second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b)
shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
7. Use of a 0.1 μF bypass capacitor connected between pins 4 and 6 is recommended.
7
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