ACPL-K73L-560E 데이터 시트보기 (PDF) - Avago Technologies

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ACPL-K73L-560E

Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature

Avago Technologies 

Powering Sequence

Speed Improvement

VDD needs to achieve a minimum level of 3V before pow- A peaking capacitor can be placed across the input cur-

ering up the output connecting component.

rent limit resistor (Figure 11) to achieve enhanced speed

Input Limiting Resistor

ACPL-W70L and ACPL-K73L are direct current driven (Fig-

ure 8), and thus eliminate the need for input power supply.

To limit the amount of current flowing through the LED, it

is recommended that a 530ohm resistor is connected in

series with anode of LED (i.e. Pin 1 for ACPL-W70L, Pin 1

performance. The value of the peaking cap is dependent

to the rise and fall time of the input signal and supply volt-

ages and LED input driving current (If). Figure 12 shows

significant improvement of propagation delay and pulse

with distortion with added 100pF peak capacitor at driv-

ing current of 6mA and 5V power supply.

and P4 for ACPL-K73L) at 5V input signal. At 3.3V input

signal, it is recommended to connect 250ohm resistor in

series with anode of LED. The recommended limiting re-

sistors is based on the assumption that the driver output

impedence is 50Ω (as shown in Figure 11).

+

Vi

-

R drv =

50Ω

Cpeak

Rlimit

VDD2

0.1µF VO

GND1

SHIELD

GND 2

35

t PLH

30

25

tPHL

With peaking cap

t PHL

Without peaking cap

20

15

10

t PLH

|PWD|

5

0

-40 -20

0

20 40 60 80 100

(i) VDD2=5V, Cpeak=100pF, Rlimit=530Ω

40

35

30

25

20

15

10

5

0

-40 -

35

Figure

11.

ConnectiPoLnH

of

peaking

capacitor

(Cpeak)

in

parallel

of

the

input

li3m0iting resistor (Rllimit) to improve speed performance

25

tPHL

With peaking cap

t PHL

Without peaking cap

20

15

10

t PLH

|PWD|

5

0

-40 -20

0

20 40 60 80 100

40

35

30

25

20

15

10

5

0

-40

tPHL

tPLH

t PHL

|PWD|

-20 0

t PLH

With peaking cap

Without peaking cap

20 40 60 80 100

(ii) VDD2=3.3V, Cpeak=100pF, Rlimit=250Ω

Figure 12. Improvement of tp and PWD with added 100pF peaking capacitor

in parallel of input limiting resistor.

11

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