ACS8509 데이터 시트보기 (PDF) - Semtech Corporation
부품명
상세내역
제조사
ACS8509 Datasheet PDF : 68 Pages
| |||
ACS8509 SETS
ADVANCED COMMUNICATIONS
FINAL
Table 6 Input Reference Source Selection and Priority Table
Port Number Channel Port Type
Number (Bin)
Input Port
Technology
SEC1
0111
TIN1
TTL/CMOS
Frequencies Supported
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz
Default (SDH): 19.44 MHz
SEC2
1000
TIN1
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz
Default (SDH): 19.44 MHz
SEC3
1011
TIN2
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (Master) (SONET): 1.544 MHz
Default (Master) (SDH): 2.048 MHz
Default (Slave) 6.48 MHz
SEC4
1101
TIN2
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 1.544 MHz
Default (SDH): 2.048 MHz
DATASHEET
Default
Priority
8
9
12/1 (Note
(ii))
14
Notes: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being
77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz,
19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH is selected using the SONSDHB pin. When the
SONSDHB pin is High SONET is selected, when the SONSDHB pin is Low SDH is selected.
(ii) Input port SEC4 is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or PORB). The default setup
of Master or Slave SEC4 priority is determined by the MSTSLVB pin.
frequency must be 8 kHz, which is indicated by setting the
lock8k bit high (bit 6 in cnfg_ref_source_frequency
register). Any input set to DivN must have the frequency
monitors disabled (If the frequency monitors are disabled,
they are disabled for all inputs regardless of the input
configurations, in this case only activity monitoring will
take place). Whilst any number of inputs can be set to use
the DivN feature, only one N can be programmed, hence
all inputs using the DivN feature must require the same
division to get to 8 kHz.
DivN Examples
To lock to 2.000 MHz:
1. The cnfg_ref_source_frequency register is set to
11XX0001 (binary) to set the DivN, lock8k bits, and
the frequency to E1/DS1. (XX = “leaky bucket” ID for
this input).
2. The cnfg_mode register (34Hex) bit 2 needs to be set
to 1 to select SONET frequencies (DS1).
3. The frequency monitors are disabled in cnfg_monitors
register (48Hex) by writing 00 to bits 0 and 1.
4. The DivN register is set to F9 Hex (249 decimal).
To lock to 10.000 MHz:
1. The cnfg_ref_source_frequency register is set to
11XX0010 (binary) to set the DivN, lock8k bits, and
the frequency to 6.48 MHz. (XX = “leaky bucket” ID for
this input).
2. The frequency monitors are disabled in cnfg_monitors
register (48Hex) by writing 00 to bits 0 and 1.
3. The DivN register is set to 4E1 Hex (1249 decimal).
Input Wander and Jitter Tolerance
The ACS8509 is compliant to the requirements of all
relevant standards, principally ITU Recommendation
G.825[15], ANSI T1.101-1999[1] and ETSI ETS 300 462-5
(1996)[4].
All reference clock inputs have a tight frequency tolerance
but a generous jitter tolerance. Pullin, hold-in and pull-out
ranges are specified for each input port in Table 7.
Minimum jitter tolerance masks are specified in Figures 3
and 4, and Tables 8 and 9, respectively. The ACS8509 will
tolerate wander and jitter components greater than those
shown in Figure 3 and Figure 4, up to a limit determined
by a combination of the apparent long-term frequency
offset caused by wander and the eye-closure caused by
jitter (the input source will be rejected if the offset pushes
Revision 2.00/January 2006 © Semtech Corp.
Page 10
www.semtech.com
Share Link: 