ACS8509 데이터 시트보기 (PDF) - Semtech Corporation
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ACS8509 Datasheet PDF : 68 Pages
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ACS8509 SETS
Synchronous Equipment Timing Source for
SONET or SDH Network Elements
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Description
Features
The ACS8509 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8509 is fully
compliant with the required international specifications
and standards.
The device supports Free-run, Locked and Holdover
modes. It also supports all three types of reference clock
source: recovered line clock, PDH network, and node
synchronization. The ACS8509 generates independent
SEC and BITS/SSU clocks, an 8 kHz Frame
Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock.
Two ACS8509 devices can be used together in a Master/
Slave configuration mode allowing system protection
against a single ACS8509 failure.
A microprocessor port is incorporated, providing access to
the configuration and status registers for device setup
and monitoring.
The ACS8509 includes a choice of edge alignment for
8 kHz input, as well as a low jitter n x E1/DS1 output
mode. The User can choose between OCXO or TCXO to
define the Stratum and/or Holdover performance
required.
Block Diagram
Suitable for Stratum 3E*, 3, 4E, 4 and SONET
Minimum Clock (SMC) or SONET/SDH Equipment
Clock (SEC) applications
Meets AT&T, ITU-T, ETSI and Telcordia specifications
Accepts four individual input reference clocks
Generates six output clocks
Supports Free-run, Locked and Holdover modes of
operation
Robust input clock source quality monitoring on all
inputs
Automatic “hit-less” source switchover on loss of input
Phase build-out for output clock phase continuity
during input switchover and mode transitions
Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, EPROM
Programmable wander and jitter tracking attenuation
0.1 Hz to 20 Hz
Support for Master/Slave device configuration
alignment and hot/standby redundancy
IEEE 1149.1 JTAG Boundary Scan
Single +3.3 V operation, +5 V I/O compatible
Operating temperature (ambient) -40°C to +85°C
Available in 100 pin LQFP package.
Lead (Pb)-free version available (ACS8509T), RoHS
and WEEE compliant.
Note...* Meets holdover requirements, lowest bandwidth 0.1 Hz.
Figure 1 Block Diagram of the ACS8509 SETS
4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Input
Port
Monitors
and
Selection
Control
4 x SEC
T4 DPLL/Freq. Synthesis
TOUT4
Selector
Digital
Divider
PFD
Loop
DTO
Filter
T0 DPLL/Freq. Synthesis
TOUT0
Selecor
Divider
Digital
PFD
Loop
DTO
Filter
6x
Output
Ports
T0 APLL
(output)
Frequency
Dividers
Programmable Outputs:
01 (PECL (default)/LVDS) =
Programmable: 19.44 MHz (default),
51.84 MHz (OC-1), 77.76 MHz and
155.52 MHz (OC-3)
02 (TTL/CMOS) = 6.48 MHz (default)
19.44 MHz and 25.92 MHz,
and E1/DS1 multiples:
1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz)
03 (TTL/CMOS) = 19.44 MHz (fixed)
04 (TTL/CMOS) =
1.544 MHz/2.048 MHz (E1/DS1)
FrSync (TTL/CMOS) =
8 kHz Frame Sync,
Fixed 50:50 MSR
MFrSync (TTL/CMOS) =
2 kHz Multiframe Sync,
Fixed 50:50 MSR
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
Microprocessor
Port
F85509 001BLOCKDIA 01
OCXO or
TCXO
Revision 2.00/January 2006 © Semtech Corp.
Page 1
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