ACS8509 SETS
ADVANCED COMMUNICATIONS
Table 3 Other Pins (cont...)
Pin Number
Symbol
I/O
75
RDY
O
Type
TTL/CMOS
76 - 83
88
AD(7:0)
O2
IO
TTLD
O
TTL/CMOS
90
O3
O
TTL/CMOS
95
O4
O
TTL/CMOS
99
MSTSLVB
I
TTLU
100
SONSDHB
I
TTLD
FINAL
DATASHEET
Description
Ready/Data Acknowledge: This pin is asserted High to indicate the device
has completed a read or write operation.
Address/Data: Multiplexed data/address bus depending on the
microprocessor mode selection. AD(0) is SDO in Serial mode.
Output Reference 2: Default 6.48 MHz. Also Dig1 (1.544 MHz/2.048 MHz
and 2, 4, 8 x), 19.44 MHz, 25.92 MHz
Output Reference 3: 19.44 MHz - fixed.
Output Reference 4: 1.544/2.048 MHz, (T4 BITS).
Master/Slave Select: Sets the initial power-up state (or state after a PORB)
of the Master/Slave selection register, Reg. 34, Bit 1. The register state
can be changed after power up by software.
SONET or SDH Frequency Select: Sets the initial power-up state (or state
after a PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit
2 and Reg. 38, Bit 5 and Bit 6. When set Low, SDH rates are selected
(2.048 MHz etc.) and when set High, SONET rates are selected (1.544 MHz
etc.) The register states can be changed after power-up by software.
Revision 2.00/January 2006 © Semtech Corp.
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