ACS8520A 데이터 시트보기 (PDF) - Semtech Corporation

부품명

상세내역

제조사

ACS8520A

Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

Semtech Corporation 

ACS8520A SETS

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Table of Contents

Section

Page

Description ................................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................................1

Features ..................................................................................................................................................................................................... 1

Pin Diagram ...............................................................................................................................................................................................4

Pin Description ...........................................................................................................................................................................................5

Introduction ................................................................................................................................................................................................8

General Description ...................................................................................................................................................................................8

Overview ............................................................................................................................................................................................8

Input Reference Clock Ports ......................................................................................................................................................... 10

Locking Frequency Modes .................................................................................................................................................... 10

PECL/LVDS/AMI Input Port Selection .................................................................................................................................. 11

Clock Quality Monitoring ................................................................................................................................................................ 12

Activity Monitoring ................................................................................................................................................................. 12

Frequency Monitoring ........................................................................................................................................................... 14

Selection of Input Reference Clock Source .................................................................................................................................. 14

Forced Control Selection ....................................................................................................................................................... 15

Automatic Control Selection ................................................................................................................................................. 15

Ultra Fast Switching .............................................................................................................................................................. 15

Fast External Switching Mode-SCRSW Pin .......................................................................................................................... 15

Output Clock Phase Continuity on Source Switchover ....................................................................................................... 16

Modes of Operation ....................................................................................................................................................................... 16

Free-run Mode ....................................................................................................................................................................... 16

Pre-locked Mode ................................................................................................................................................................... 16

Locked Mode ......................................................................................................................................................................... 16

Lost-phase Mode ................................................................................................................................................................... 17

Holdover Mode ...................................................................................................................................................................... 17

Pre-locked2 Mode ................................................................................................................................................................. 19

DPLL Architecture and Configuration ........................................................................................................................................... 19

TO DPLL Main Features ........................................................................................................................................................ 20

T4 DPLL Main Features ........................................................................................................................................................ 20

TO DPLL Automatic Bandwidth Controls .............................................................................................................................. 20

Phase Detectors .................................................................................................................................................................... 21

Phase Lock/Loss Detection .................................................................................................................................................. 21

Damping Factor Programmability ......................................................................................................................................... 21

Local Oscillator Clock ............................................................................................................................................................ 22

Output Wander ...................................................................................................................................................................... 23

Jitter and Wander Transfer ................................................................................................................................................... 25

Phase Build-out ..................................................................................................................................................................... 25

Input to Output Phase Adjustment ....................................................................................................................................... 26

Input Wander and Jitter Tolerance ....................................................................................................................................... 26

Using the DPLLs for Accurate Frequency and Phase Reporting ........................................................................................ 28

Configuration for Redundancy Protection .................................................................................................................................... 29

Alignment of Priority Tables in Master and Slave ACS8520A ............................................................................................ 30

T4 Generation in Master and Slave ACS8520A .................................................................................................................. 30

Alignment of the Output Clock Phases in Master and Slave ACS8520A .......................................................................... 30

MFrSync and FrSync Alignment-SYNC2K ............................................................................................................................. 31

Output Clock Ports ......................................................................................................................................................................... 32

PECL/LVDS/AMI Output Port Selection ............................................................................................................................... 32

Output Frequency Selection and Configuration .................................................................................................................. 32

Microprocessor Interface ....................................................................................................................................................................... 43

Introduction to Microprocessor Modes ........................................................................................................................................ 43

Motorola Mode ...................................................................................................................................................................... 44

Intel Mode .............................................................................................................................................................................. 46

Multiplexed Mode .................................................................................................................................................................. 48

Serial Mode ............................................................................................................................................................................ 50

EPROM Mode ......................................................................................................................................................................... 52

Revision 1.00/September 2007© Semtech Corp.

Page 2

www.semtech.com

Share Link: