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ACS8520A

Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems

Semtech Corporation 

ACS8520A SETS

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Introduction

The ACS8520A is a highly integrated, single-chip solution

for the SETS function in a SONET/SDH Network Element,

for the generation of SEC and Frame/MultiFrame

Synchronization pulses. Digital Phase Locked Loop (DPLL)

the external oscillator module. This second key advantage

confines all temperature critical components to one well

defined and pre-calibrated module, whose performance

can be chosen to match the application; for example an

TCXO for Stratum 3 applications.

and direct digital synthesis methods are used in the

All performance parameters of the DPLLs are

device so that the overall PLL characteristics are very

stable and consistent compared to traditional analog

programmable without the need to understand detailed

PLL equations. Bandwidth, damping factor and lock range

PLLs.

can all be set directly, for example. The PLL bandwidth

In Free-run mode, the ACS8520A generates a stable, low-

noise clock signal at a frequency to the same accuracy as

the external oscillator, or it can be made more accurate

via software calibration to within ±0.02 ppm. In Locked

mode, the ACS8520A selects the most appropriate input

reference source and generates a stable, low-noise clock

signal locked to the selected reference. In Holdover mode,

the ACS8520A generates a stable, low-noise clock signal,

adjusted to match the last known good frequency of the

last selected reference source. A high level of phase and

frequency accuracy is made possible by an internal

resolution of up to 54 bits and internal Holdover accuracy

of up to 7.5 x 10-14 (instantaneous). In all modes, the

frequency accuracy, jitter and drift performance of the

clock meet the requirements of ITU G.736[7], G.742[8],

G783[9], G.812[10], G.813[11], G.823[13],G.824[14] and

Telcordia GR-253-CORE[17] and GR-1244-CORE[19].

The ACS8520A supports all three types of reference clock

can be set over a wide range, 0.1 Hz to 70 Hz in 18 steps,

to cover all SONET/SDH clock synchronization

applications.

The ACS8520A supports protection. Two ACS8520A

devices can be configured to provide protection against a

single ACS8520A failure. The protection maintains

alignment of the two ACS8520A devices (Master and

Slave) and ensures that both ACS8520A devices maintain

the same priority table, choose the same reference input

and generate the T0 clock, the 8 kHz Frame

Synchronization clock and the 2 kHz Multi-Frame

Synchronization clock with the same phase. The

ACS8520A includes a multi-standard microprocessor

port, providing access to the configuration and status

registers for device setup and monitoring.

General Description

source: recovered line clock, PDH network

synchronization timing, and node synchronization. The

Overview

ACS8520A generates independent T0 and T4 clocks, an 8

kHz Frame Synchronization clock and a 2 kHz Multi-Frame

Synchronization clock.

The following description refers to the Block Diagram

(Figure 1 on page 1).

One key architectural advantage that the ACS8520A has

over traditional solutions is in the use of DPLL technology

for precise and repeatable performance over temperature

or voltage variations and between parts. The overall PLL

bandwidth, loop damping, pull-in range and frequency

The ACS8520A SETS device has 14 input clocks,

generates 11 output clocks, and has a total of 55 possible

output frequencies. There are two main paths through the

device: T0 and T4. Each path has an independent DPLL

and APLL pair.

accuracy are all determined by digital parameters that The T0 path is a high quality, highly configurable path

provide a consistent level of performance. An Analog PLL designed to provide features necessary for node timing

(APLL) takes the signal from the DPLL output and provides synchronization within a SONET/SDH network. The T4

a lower jitter output. The APLL bandwidth is set four orders path is a simpler and less configurable path designed to

of magnitude higher than the DPLL bandwidth. This

give a totally independent path for internal equipment

ensures that the overall system performance still

synchronization. The device supports use of either or both

maintains the advantage of consistent behavior provided paths, either locked together or independent.

by the digital approach.

Of the 14 input references, two are AMI composite clock,

The DPLLs are clocked by the external Oscillator module two are LVDS/PECL and the remaining ten are TTL/CMOS

(TCXO or OCXO) so that the Free-run or Holdover

compatible inputs. All the TTL/CMOS are 3 V compatible

frequency stability is only determined by the stability of (with clamping if required by connecting the VDDCLMP

Revision 1.00/September 2007© Semtech Corp.

Page 8

www.semtech.com

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