ACS8522AT 데이터 시트보기 (PDF) - Semtech Corporation
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ACS8522AT Datasheet PDF : 118 Pages
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ACS8522A SETS LITE
Synchronous Equipment Timing Source for
Stratum 3/4E/4 and SMC Systems
ADVANCED COMMSUN&ICSAETNIOSNINSG
FINAL
DATASHEET
Description
Features
The ACS8522A is a highly integrated, single-chip solution for the
Synchronous Equipment Timing Source (SETS) function in a
SONET or SDH Network Element. The device generates SONET
or SDH Equipment Clocks (SEC) and Frame Synchronization
clocks. The ACS8522A is fully compliant with the required
international specifications and standards.
Suitable for Stratum 3, 4E, 4 and SONET Minimum
Clock (SMC) or SONET/SDH Equipment Clock (SEC)
applications (to Telcordia 1244-CORE[19] Stratum 3
and GR-253[17], and ITU-T G.813[11] Options Ι and ΙΙ
specifications).
The device supports Free-run, Locked and Holdover modes,
with mode selection controlled either automatically by an
internal state machine or forced by register configuration.
The ACS8522A accepts up to four independent input SEC
reference clock sources from Recovered Line Clock, PDH
network, and Node Synchronization. The ACS8522A generates
independent SEC and BITS clocks, an 8 kHz Frame
Synchronization clock and a 2 kHz Multi-Frame Synchronization
clock, both with programmable pulse width and polarity.
The ACS8522A includes a Serial Port, which can be SPI
compatible, providing access to the configuration and status
registers for device setup.
The ACS8522A supports IEEE 1149.1[5] JTAG boundary scan.
Accepts four individual input reference clocks, all with
robust input clock source quality monitoring.
Simultaneously generates four output clocks, plus two
Sync pulse outputs.
Absolute Holdover accuracy better than 3 x 10-10
(manual), 7.5 x 10-14 (instantaneous); Holdover
stability defined by choice of external XO.
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps.
Automatic hit-less source switchover on loss of input
Serial SPI compatible interface.
Output phase adjustment in 6 ps steps up to ±200 ns
The User can choose between OCXO or TCXO to define the
Stratum and/or Holdover performance required.
IEEE 1149.1[5] JTAG Boundary Scan.
Available in LQFP 64-pin package.
Single 3.3 V operation.
Block Diagram
Lead (Pb)-free version available (ACS8522AT), RoHS
and WEEE compliant.
Figure 1 Block Diagram of the ACS8522A SETS LITE
Inputs: 4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Input
Port
Monitors
and
Selection
Control
4 x SEC
T4 DPLL/Freq. Synthesis
Digital
T4 DPLL
Optional
PFD
Selector
Divider, 1/n
n = 1 to 214
Loop
Filter
DTO
T0 DPLL/Freq. Synthesis
T0 DPLL
Optional
Selector
Divider, 1/n
n = 1 to 214
PFD
Digital
Loop
DTO
Filter
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
OCXO or
TCXO
Revision 1.00/September 2007 © Semtech Corp.
Serial
Port
Page 1
T4 Output
APLL
Frequency
Dividers
T0 Output
APLL
Frequency
Dividers
T0 Feedback
APLL
Output
Ports
O1
to
O4
Output O1: PECL/LVDS
Outputs O2 - 04: TTL
Programmable;
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
2 kHz
8 kHz
and OC-N* rates
FrSync
&
MFrSync
8 kHz
(FrSync)
2 kHz
(MFrSync)
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
F8522P_001BLOCKDIA_04
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