ACS8522BT 데이터 시트보기 (PDF) - Semtech Corporation

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ACS8522BT

Synchronous Equipment Timing Source for Stratum 3/4E/4, SMC and Ethernet Systems

Semtech Corporation 

ACS8522BT eSETS

ADVANCED COMMS & SENSING

FINAL

DATASHEET

The DPLL of the T0 path always produces an output at

77.76 MHz to feed the APLL, regardless of the frequency

selected at the output pins. The T4 path can be operated

at a number of frequencies. This is to enable the

generation of extra output frequencies, which cannot be

easily related to 77.76 MHz. When the T4 path is selected

to lock to the T0 path, the T4 DPLL locks to the 8 kHz from

the T0 DPLL. This is because all of the frequencies of

operation of the T4 path can be divided to 8 kHz and this

will ensure synchronization of all the frequencies within

the two paths.

On power-up or by reset, the default will be set by the state

of the SONSDHB pin (pin 64). Specific frequencies and

priorities are set by configuration.

The frequency selection is programmed via the

cnfg_ref_source_frequency register (Reg. 22, 22, 27 and

28).

Locking Frequency Modes

There are three locking frequency modes that can be

configured:

The outputs of both DPLLs are connected to multiplying

and filtering APLLs. The outputs of the APLLs are divided,

making a number of frequencies simultaneously available

for selection at the output clock ports. The various

combinations of DPLL, APLL and divider configurations

allow for generation of a comprehensive set of

frequencies as listed in Table 12.

To synchronize the lower output frequencies when the T0

PLL is locked to a high frequency reference input, an

additional input is provided. The SYNC2K pin (pin 28) is

used to reset the dividers that generate the 2 kHz and

8 kHz outputs such that the output 2/8 kHz clocks are

lined up with the input 2 kHz. This synchronization

method could allow for example, a master and a slave

device to be in precise alignment.

The ACS8522BT also supports Sync pulse references of

4 kHz or 8 kHz, although frequencies lower than the Sync

pulse reference may not necessarily be in phase.

Input Reference Clock Ports

Table 4 gives details of the input reference ports, showing

the input technologies and the range of frequencies

supported on each port; the default spot frequencies and

default priorities assigned to each port on power-up or by

reset are also shown.

Direct Lock

Lock 8k

DivN

Direct Lock Mode

In Direct Lock Mode, the internal DPLL can lock to the

selected input at the spot frequency of the input, for

example 19.44 MHz performs the DPLL phase

comparisons at 19.44 MHz.

In Lock8K and DivN modes an internal divider is used

prior to the DPLL to divide the input frequency before it is

used for phase comparisons in the DPLL.

Lock8K Mode

Lock8K mode automatically sets the divider parameters

to divide the input frequency down to 8 kHz. Lock8K can

only be used on the supported spot frequencies (see

Table 4 Note(i)).

Lock8k mode is enabled by setting the Lock8k bit (Bit 6)

in the appropriate cnfg_ref_source_frequency register

location. Using lower frequencies for phase comparisons

in the DPLL results in a greater tolerance to input jitter. It

is possible to choose which edge of the input reference

clock to lock to, by setting 8K edge polarity (Bit 2 of

Reg. 03, test_register1.

Note that SDH and SONET networks use different default

frequencies; the network type is pin-selectable (using

either the SONSDHB pin or via software). Specific

frequencies and priorities are set by configuration.

The input ports are fully interchangeable.

SDH and SONET networks use different default

frequencies; the network type is selectable using

cnfg_input_mode Reg. 34, Bit 2 ip_sonsdhb.

for SONET, ip_sonsdhb = 1

for SDH, ip_sonsdhb = 0

Revision 1.00/April 2010© Semtech Corp.

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