ACS8522BT 데이터 시트보기 (PDF) - Semtech Corporation
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ACS8522BT
Semtech Corporation
ACS8522BT Datasheet PDF : 122 Pages
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ACS8522BT eSETS
ADVANCED COMMS & SENSING
Table 3 Other Pins
FINAL
DATASHEET
Pin Number
Symbol
I/O
5
INTREQ
O
6
REFCLK
I
13
SRCSW
I
17
FrSync
O
18
MFrSync
O
19, 20
O1POS, O1NEG O
28
SYNC2K
I
29
SEC1
I
30
SEC2
I
33
SEC3
I
34
SEC4
I
37
TRST
I
41
TMS
I
42
CLKE
I
43
SDI
I
44
CSB
I
47
SCLK
I
48
PORB
I
49
TCK
I
50
TDO
O
51
TDI
I
52
SDO
O
55
O2
O
56
O3
O
59
O4
O
64
SONSDHB
I
Type
TTL/CMOS
TTL
TTLD
TTL/CMOS
TTL/CMOS
LVDS/PECL
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLU
TTLD
TTLU
TTLD
TTL/CMOS
TTLD
TTLD
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTLD
Description
Active High/Low software interrupt request output.
12.800 MHz reference clock (refer to Local Oscillator Clock).
Force fast source switching on SEC1 and SEC2.
8 kHz Frame Sync reference output.
2 kHz Multi-Frame Sync reference output.
Output reference, programmable, default 38.88 MHz, LVDS.
Multi-Frame Sync 2kHz input.
Input reference, programmable, default 8 kHz.
Input reference, programmable, default 8 kHz.
Input reference, programmable, default 19.44 kHz.
Input reference, programmable, default 19.44 kHz.
JTAG control reset Input.
1 = enable JTAG boundary scan mode.
0 = boundary scan standby mode allowing correct device operation.
If not used connect to GND or leave floating.
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge
of TCK. If not used connect to VDD or leave floating.
SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling
edge of SCLK to be active.
Microprocessor Interface Address: Serial Data Input.
Chip Select (Active Low): This pin is asserted Low by the microprocessor
to enable the microprocessor interface.
Serial Data Clock. When this pin goes High data is latched from SDI pin.
Power-On Reset: Master reset. If PORB is forced Low, all internal states
are reset back to default values.
JTAG Clock: Boundary Scan clock input.
JTAG Output: Serial test data output. Updated on falling edge of TCK.
JTAG Input: Serial test data Input. Sampled on rising edge of TCK.
Interface Address: SPI compatible Serial Data Output.
Output reference 2, programmable, default 38.88 MHz.
Output reference 3, programmable, default 19.44 MHz.
Output reference 4, programmable, default 1.544/2.048 MHz (BITS).
Sets the initial power-up or PORB state of the SONET/SDH frequency
selection registers, Reg. 34 Bit 2, and Reg. 38 Bits 5 and 6. When set
Low, SDH rates are selected (2.048 MHz etc.), and when set High,
SONET rates are selected (1.544 MHz etc.). The register states can be
changed after power-up by software.
Revision 1.00/April 2010© Semtech Corp.
Page 7
www.semtech.com
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