ACS8522BT 데이터 시트보기 (PDF) - Semtech Corporation

부품명

상세내역

제조사

ACS8522BT

Synchronous Equipment Timing Source for Stratum 3/4E/4, SMC and Ethernet Systems

Semtech Corporation 

ACS8522BT eSETS

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Introduction

The ACS8522BT is a highly integrated, single-chip

solution for the SETS function in a SONET/SDH/Ethernet

network element, for the generation of SEC and

Frame/MultiFrame sync pulses. Digital phase locked loop

(DPLL) and direct digital synthesis methods are used in

An Analog PLL (APLL) takes the signal from the DPLL

output and provides a lower jitter output. The APLL

bandwidth is set four orders of magnitude higher than the

DPLL bandwidth. This ensures that the overall system

performance still maintains the advantage of consistent

behavior provided by the digital approach.

the device so that the overall PLL characteristics are very The DPLLs are clocked by the external Oscillator module

stable and consistent compared to traditional analog

(TCXO or OCXO) so that the Free-run or Holdover

PLLs.

frequency stability is only determined by the stability of

In free-run mode, the ACS8522BT generates a stable, low-

noise clock signal at a frequency to the same accuracy as

the external oscillator, or it can be made more accurate

via software calibration to within 0.02 ppm

In locked mode, the ACS8522BT selects the most

appropriate input reference source and generates a

stable, low-noise clock signal locked to the selected

reference.

In holdover mode, the ACS8522BT generates a stable,

low-noise clock signal, adjusted to match the last known

good frequency of the last selected reference source. A

high level of phase and frequency accuracy is made

possible by an internal resolution of up to 54 bits and

internal holdover accuracy of 0.0012 ppb (1.2 x 10-12).

In all modes, the frequency accuracy, jitter and drift

the external oscillator module. This second key advantage

confines all temperature critical components to one well

defined and pre-calibrated module, whose performance

can be chosen to match the application; for example an

TCXO for Stratum 3 applications.

All performance parameters of the DPLLs are

programmable without the need to understand detailed

PLL equations. Bandwidth, damping factor and lock range

can all be set directly, for example. The PLL bandwidth

can be set over a wide range, 0.1 Hz to 70 Hz in 18 steps,

to cover all SONET/SDH clock synchronization

applications.

The ACS8522BT includes a serial port, providing access

to the configuration and status registers for device setup

and monitoring.

performance of the clock meet the requirements of:

ITU G.736

G.742

G783

G.812

G.813

G.823

G.824 and Telcordia GR-253-CORE

GR-1244-CORE

ITU-T G.8262 (Draft).

The ACS8522BT supports all three types of reference

clock source: recovered line clock, PDH network

synchronization timing and node synchronization. The

ACS8522BT generates independent T0 and T4 clocks, an

8 kHz Frame Synchronization clock and a 2 kHz

Multi-Frame Synchronization clock.

A significant architectural advantage of the ACS8522BT

over traditional solutions is the use of DPLL technology for

precise and repeatable performance over temperature or

voltage variations, and between parts. The overall PLL

bandwidth, loop damping, pull-in range and frequency

accuracy are all determined by digital parameters that

provide a consistent level of performance.

Revision 1.00/April 2010© Semtech Corp.

Page 8

www.semtech.com

Share Link: