ACS8526T 데이터 시트보기 (PDF) - Semtech Corporation

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ACS8526T

Line Card Protection Switch for PDH, SONET or SDH Systems

Semtech Corporation 

ADVANCED COMMUNICATIONS

Figure 3 Inactivity and Irregularity Monitoring

FINAL

Inactivities/Irregularities

ACS8526 LC/P LITE

DATASHEET

Reference

Source

Leaky

Bucket

Response

Programmable Fall Slopes

bucket_size

upper_threshold

lower_threshold

(all programmable)

Alarm

Leaky Bucket Timing

The time taken (in seconds) to raise an inactivity alarm on

an SEC that has previously been fully active (Leaky Bucket

empty) will be:

(cnfg_upper_threshold) / 8

If an input is intermittently inactive then this time can be

longer. The default setting of cnfg_upper_threshold is 6,

therefore the default time is 0.75 s.

The time taken (in seconds) to cancel the activity alarm on

a previously completely inactive SEC is calculated, for a

particular Leaky Bucket, as:

[2 (a) x (b - c)]/ 8

where:

a = cnfg_decay_rate

b = cnfg_bucket_size

c = cnfg_lower_threshold

The default setting is shown in the following:

[21 x (8 - 4)] /8 = 1.0 secs

Fast Activity Monitor

Anomalies on the selected clock have to be detected as

they occur and the PLL must be temporarily isolated until

the clock is once again pure. The SEC activity monitor

cannot be used for this because the high degree of

accuracy required dictates that the process be slow. To

achieve the immediacy required, the PLL uses an

alternative mechanism. The phase locked loop itself

contains an additional fast activity monitor such that

F8530D_026Inact_Irreg_Mon_02

within approximately two missing input clock cycles, a

no-activity flag is raised and the DPLL is frozen in Digital

Holdover mode. This flag generates LOS (Loss of Signal)

alarm on pin LOS_ALARM.

With the DPLL in Digital Holdover mode it is isolated from

further disturbances. If the input becomes active again

then the DPLL will continue to lock to the input, with little

disturbance.

Phase Locked Loops (PLLs)

This section is in four parts;

z Overview description of the PLLs

z Architectural description, introducing the sub-blocks

and their interconnection options for different

frequency selection and jitter filtering

z Description of PLL controls- phase error detector

options, Loop bandwidth and damping selection

z DPLL summary feature list.

PLL Overview

The PLL circuitry comprises the following blocks shown in

Figure 1: Two Digital PLLs (DPLL1 and DPLL2), two output

multiplying and filtering Analog PLLs (APLL1 and APLL2),

output frequency dividers in an Output Port Frequency

Selection block, a synthesis block, multiplexers MUX1 and

MUX2, and a feedback Analog PLL (APLL3).

These functional blocks, and their interconnections, are

highly configurable, via register control, which provides a

Revision 4.01/June 2006 © Semtech Corp.

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