ACS8527 데이터 시트보기 (PDF) - Semtech Corporation
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ACS8527 Datasheet PDF : 22 Pages
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ACS8527 MUXPLL
ADVANCED COMMUNICATIONS
Electrical Specifications
FINAL
DATASHEET
JTAG
The JTAG connections on the ACS8527 allow a full
boundary scan to be made. The JTAG implementation is
fully compliant to IEEE 1149.1[4], with the following minor
exceptions, and the user should refer to the standard for
further information.
1. The output boundary scan cells do not capture data
from the core, and so do not support INTEST. However
this does not affect board testing.
2. In common with some other manufacturers, pin TRST
is internally pulled Low to disable JTAG by default. The
standard is to pull High. The polarity of TRST is as the
standard: TRST High to enable JTAG boundary scan
mode, TRST Low for normal operation.
The JTAG timing diagram is shown in Figure 3.
Figure 3 JTAG Timing
Over-voltage Protection
The ACS8527 may require Over-voltage Protection on
input reference clock ports according to ITU
recommendation K.41[10]. Semtech protection devices
are recommended for this purpose (see Protection
section on Semtech website: http://www.semtech.com.
ESD Protection
Suitable precautions should be taken to protect against
electrostatic damage during handling and assembly. This
device incorporates ESD protection structures that
protect the device against ESD damage at ESD input
levels up to at least +/2kV using the Human Body Model
(HBD) MIL-STD-883D Method 3015.7, for all pins.
Latchup Protection
This device is protected against latchup for input current
pulses of magnitude up to at least ±100 mA to JEDEC
Standard No. 78 August 1997.
tCYC
TCK
TMS
TDI
tSUR tHT
tDOD
TDO
F8110D_022JTAGTiming_01
Table 7 JTAG Timing (for use with Figure 3)
Parameter
Symbol
Cycle Time
tCYC
TMS/TDI to TCK rising edge time
tSUR
TCK rising to TMS/TDI hold time
tHT
TCK falling to TDO valid
tDOD
Minimum
50
3
23
-
Typical
-
-
-
-
Maximum
-
-
-
5
Units
ns
ns
ns
ns
Revision 4.01/June 2006 © Semtech Corp.
Page 10
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