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ACS8527T

Line Card Protection Switch for PDH, SONET or SDH Systems

Semtech Corporation 

ACS8527 MUXPLL

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Introduction

The ACS8527 is a highly integrated, single-chip solution

for protection switching of two SEC inputs from, for

example, Master and Slave SETS clock cards sources, for

Line Cards in a SONET or SDH Network Element. The

ACS8527 has fast activity monitors on the SEC clock

inputs.

initial lock (with no input reference) or in Digital Holdover,

the frequency stability is only determined by the stability

of the external oscillator module. This gives the key

advantage of confining all temperature critical

components to one well defined and pre-calibrated

oscillator module, whose performance can be chosen to

match the application.

The ACS8527 is a standalone part where all input and

output frequencies are set by external control using the

An Evaluation board is available for device introduction.

This has its own documentation “ACS8527-EVB”.

IP_FREQ, OP_FREQ and SONSDHB pins.

The SRCSW pin is used to select one of the two SEC inputs

to lock to. The SRCSW pin must remain High for an

initialization period of at least 251 ms following power-up

or reset (251 ms after the PORB signal has gone High).

SRCSW Low immediately after a power-up or reset is not

supported.

The ACS8527 has two SEC inputs from which it can

generate independent clocks on outputs 01 and 02 (11

possible output clock frequencies). In addition, there are

two Sync outputs; 8 kHz Frame Synchronization (FrSync)

signal and a 2 kHz Multi-Frame Synchronization

(MFrSync) signal.

General Description

The following description refers to the Block Diagram

(Figure 1 on page 1).

Inputs

The ACS8527 SETS device has two TTL/CMOS compatible

SEC input ports. They are 3 V and 5 V compatible (with

clamping if required by connecting the VDD5V pin). Refer

to the “Electrical Specifications” on page 10 for more

information on electrical compatibility.

Initially the ACS8527 generates a stable, low-noise clock

signal at a frequency to the same accuracy as the external

oscillator. The device always attempts to lock to one of its

inputs (according to the value on the SRCSW pin). Once

locked to a reference the accuracy of the output clock is

determined directly by the accuracy of the input

reference. In the absence of any input references the

device simply maintains its most recent frequency in a

Digital Holdover mode. However, as soon as the DPLL

(Digital Phase Locked Loop) detects an input presence, it

will attempt to lock to it and will not “qualify” it first. As

soon as the DPLL detects a failure on the input, the DPLL

freezes its operating frequency and raises the LOS alarm

on device pin LOS_ALARM.

The overall PLL (Phased Locked Loop) loop bandwidth,

damping, pull-in range and frequency accuracy are all

determined by fixed digital parameters that provide a

consistent level of performance. An Analog PLL (APLL)

takes the signal from the DPLL output and provides a

lower jitter output. The APLL bandwidth is set four orders

of magnitude higher than the DPLL bandwidth. This

ensures that the overall system performance still

maintains the advantage of consistent behavior provided

by the digital approach. The DPLLs are clocked by the

external oscillator module (TCXO or XO) so that prior to

Input frequencies supported range from 8 kHz to

77.76 MHz. Common E1, DS1, OC-3 and sub-divisions are

supported as spot frequencies that the DPLLs will directly

lock to.

In addition to the SEC inputs, there are four configuration

pins IP_FREQ [2:0] and SONSDHB used to configure the

input to expect a particular input frequency (same value

applies to both inputs), and a control pin SRCSW for

switching between SEC1 and SEC2 as the selected input

reference to which the device tries to lock.

Preconfiguring Inputs - Expected Input Frequency

The inputs SEC1 and SEC2 must be preconfigured to

expect a particular input frequency. This can be selected

from a range of spot frequencies by configuring the

hardware pins IP_FREQ [2:0] and SONSDHB, which are

read on reset.

The combined pin states of IP_FREQ [2:0] and SONSDHB

represent a 4-bit word which addresses a particular

frequency value as given in Table 4.

The frequency selected by the hardware configuration is

always applied to both inputs on Power-up or Reset, so

both will be preconfigured to expect the same frequency.

Revision 4.01/June 2006 © Semtech Corp.

Page 6

www.semtech.com

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