ACT-7000SC-150F17C 데이터 시트보기 (PDF) - Aeroflex Corporation
부품명
상세내역
제조사
ACT-7000SC-150F17C Datasheet PDF : 25 Pages
| |||
Table 6 – Cache Attributes
Attribute
Instruction
Data
Secondary
Size
Associativity
16KB
4-way
16KB
4-way
256KB
4-way
Replacement Algorithm.
Line size
Index
Tag
Write policy
read policy
read order
cyclic
32 byte
vAddr 11..0
pAddr 35..12
n.a.
n.a.
critical word first
cyclic
cyclic
32 byte
32 byte
vAddr 11..0
pAddr 15..0
pAddr 35..12
pAddr 35..16
write-back, write-through
block write-back, bypass
non-blocking (2 outstanding) non-blocking (data only, 2
outstanding)
critical word first
critical word first
write order
NA
sequential
sequential
miss restart following:
complete line
first double (if waiting for
n.a.
data)
Parity
per word
per byte
per doubleword
Cache Locking
The ACT 7000SC allows critical code or data
fragments to be locked into the primary and
secondary caches. The user has complete control
over what locking is performed with cache line
granularity. For instruction and data fragments in the
primaries, locking is accomplished by setting either or
both of the cache lock enable bits in the CP0 ECC
register, specifying the set via a field in the CP0 ECC
register, and then executing either a load instruction
or a Fill_I cache operation for data or instructions
respectively. Only two sets are lockable within each
cache: set A and set B. Locking within the secondary
works identically to the primaries using a separate
secondary lock enable bit and the same set selection
field. As with the primaries, only two sets are lockable:
sets A and B. Table 7 summarizes the cache locking
capabilities.
Table 7 – Cache Locking Control
movement operations in the embedded environment,
the ACT 7000SC significantly improves the speed of
operation of certain critical cache management
operations as compared with the R5000 and R4000
families. In particular, the speed of the
Hit-Write-back-Invalidate and Hit-Invalidate cache
operations has been improved in some cases by an
order of magnitude over that of the earlier families.
Table 8 compares the ACT 7000SC with the R4000
and R5000 processors.
Table 8 – Penalty Cycle
Operation
Condition
Penalty
ACT 7000S R4000/R500
C
0
Hit-Writebac Miss
0
7
k-Invalidate
Hit-Clean
3
12
Cache
Primary I
Lock
Enable
Set Select
ECC[27] ECC[28]=0→A
ECC[28]=1→B
Activate
Fill_I
Hit-Dirty
Hit-Invalidate Miss
Hit
3+n
14+n
0
7
2
9
Primary D ECC[26] ECC[28]=0→A
ECC[28]=1→B
Secondary ECC[25] ECC[28]=0→A
ECC[28]=1→B
Cache Management
To improve the performance of
Aeroflex Circuit Technology
Load/Store
Fill_I or
Load/Store
critical data
10
For the Hit-Dirty case of Hit-Writeback-Invalidate, if
the writeback buffer is full from some previous cache
eviction then n is the number of cycles required to
empty the write-back buffer. If the buffer is empty then
n is zero.
The penalty value is the number of processor
cycles beyond the one cycle required to issue the
instruction that is required to implement the operation.
SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700
Share Link: 