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AD13280AF(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD13280AF Datasheet PDF : 20 Pages
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AD13280–SPECIFICATIONS (AVCC = +5 V, AVEE = –5 V, DVCC = +3.3 V; applies to each ADC with Front-End
Amplifier unless otherwise noted.)
Parameter
Temp
RESOLUTION
DC ACCURACY1
No Missing Codes
Offset Error
Offset Error Channel Match
Gain Error2
Gain Error Channel Match
Full
25°C
Full
Full
25°C
Full
25°C
Max
Min
SINGLE-ENDED ANALOG INPUT
Input Voltage Range
AMP-IN-X-1
AMP-IN-X-2
Input Resistance
AMP-IN-X-1
AMP-IN-X-2
Capacitance
Analog Input Bandwidth3
Full
Full
Full
Full
25°C
Full
DIFFERENTIAL ANALOG INPUT
Analog Signal Input Range
A+IN to A–IN and B+IN to B–IN4
Input Impedance
Analog Input Bandwidth
Full
25°C
Full
ENCODE INPUT (ENC, ENC)1
Differential Input Voltage
Differential Input Resistance
Differential Input Capacitance
Full
25°C
25°C
SWITCHING PERFORMANCE
Maximum Conversion Rate5
Minimum Conversion Rate5
Aperture Delay (tA)
Aperture Delay Matching
Aperture Uncertainty (Jitter)
ENCODE Pulsewidth High at Max Conversion Rate
ENCODE Pulsewidth Low at Max Conversion Rate
Output Delay (tOD)
Encode, Rising to Data Ready, Rising Delay
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
Full
SNR1, 6
Analog Input @ 10 MHz
Analog Input @ 21 MHz
Analog Input @ 37 MHz
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
SINAD1, 7
Analog Input @ 10 MHz
Analog Input @ 21 MHz
Analog Input @ 37 MHz
25°C
Min
Max
25°C
Min
Max
25°C
Min
Max
Test
Level
IV
I
VI
VI
I
VI
I
VI
VI
V
V
IV
IV
V
V
V
V
V
IV
V
V
VI
IV
V
IV
V
IV
IV
V
V
I
II
II
I
II
II
I
II
II
I
II
II
I
II
II
I
II
II
Mil
Subgroup
12
1
2, 3
1, 2, 3
1
2, 3
1
2
3
12
12
12
4, 5, 6
12
12
12
12
4
6
5
4
6
5
4
6
5
4
6
5
4
6
5
4
6
5
AD13280AZ/BZ
Min Typ
Max
12
Guaranteed
–2.2 ± 1.0
+2.2
–2.2 ± 1.0
+2.2
–1.0 ± 0.1
+1.0
–3
–1.0
+1
–5.0 ± 2.0
+5.0
–1.5 ± 0.5
+1.5
–3.0 ± 1.0
+3.0
–5
± 1.0
+5
± 0.5
± 1.0
99
100
101
198 200
202
4.0
7.0
100
±1
618
50
0.4
10
2.5
80
20
1.5
250
500
0.3
4.75 6.25
8
4.75 6.25
8
5
8.5
67.5 70
64.5
67.5
67.5 70
64
67.5
63.5 65
61.5
63.5
67
69
63.5
67
65
68.5
63
65
54.5 59
53
54.5
Unit
Bits
% FS
% FS
%
% FS
% FS
%
%
%
V
V
pF
MHz
V
MHz
V p-p
k
pF
MSPS
MSPS
ns
ps
ps rms
ns
ns
ns
ns
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
–2–
REV. 0

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