AD1385 데이터 시트보기 (PDF) - Analog Devices

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AD1385

16-Bit 500 kHz Wide Temperature Range Sampling ADC

Analog Devices 

AD1385

Figure 17. Start-Convert Controlled Conversion Timing

Figure 18. Free Running Conversion Timing

At this point a new conversion will be initiated. The minimum

setup and hold times for Start Convert relative to the rising

clock edge are 10 ns. Start Convert transitions should not be

placed in the window which begins 100 ns (one clock period)

after the rising edge of Hold Command Out and which ends

1300 ns (thirteen clock periods) after this rising edge (see Fig-

ure 17). This minimizes internal coupling between Start Con-

vert and sensitive internal circuit nodes.

rising edge of Start Convert places the T/H into Hold mode; the

A/D conversion cycle begins with the first rising clock edge after

the Start Convert transition, and Start Convert must remain

high during at least one rising clock edge in order to begin the

conversion. The width of Start Convert should be either less

than 150 ns or greater than 1400 ns to minimize coupling be-

tween the falling edge of Start Convert and sensitive internal

nodes. In asynchronous operation the T/H will remain in Hold

Transmission line effects at the Start Convert input should be

considered when designing circuit boards for the AD1385. A se-

ries termination resistor of 50 Ω to 100 Ω is recommended when

the source of Start Convert is more than a few inches away from

the AD1385. This will control reflections and transients which

could otherwise degrade the part’s performance.

Asynchronous Operation

In synchronous operation the T/H is placed into Hold mode by

the first rising clock edge after Start Convert goes high. This

mode of operation provides maximum rejection of system clock

noise. Some applications may require the AD1385 to operate

asynchronously, that is, with the Start Convert input directly

controlling the track-to-hold transition. This may be achieved

using a 2-input OR gate connected as shown in Figure 19. The

Figure 19. Connecting the AD1385 to Sample the Input

Signal Asynchronously from the Clock

–10–

REV. 0

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