AD1385 데이터 시트보기 (PDF) - Analog Devices
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AD1385 Datasheet PDF : 20 Pages
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AD1385
Parameter
OUTPUT CODING
INTERNAL REFERENCE
Voltage
Current
Drift
TEMPERATURE RANGE, CASE
Specified
Storage
POWER REQUIREMENTS
Specified Operating Range
± VS
+VDD
–VSS
Current Drains
+VS
–VS
+VDD
–VSS
Power Dissipation
AD1385KD
Min
Typ
Max
AD1385TD
Min
Typ
Max
Complementary Offset Binary or Complementary Twos Complement
9.990
2
5
5
10.010
15
9.990
2
5
5
10.010
15
0
+70
–55
+125
–65
+150
–65
+150
Units
V
mA
ppm/°C
°C
°C
14.25
4.75
–5.25
52
48
104
148
2.76
15.75
5.25
–4.75
80
75
160
200
4.125
14.25
4.75
–5.25
52
48
104
148
2.76
15.75
5.25
–4.75
80
75
160
200
4.125
V
V
V
mA
mA
mA
mA
Watts
NOTES
1Integral linearity is inferred from FFTs. Differential linearity is derived from histograms.
2Performance over temperature is specified at the temperature at which the last calibration was performed.
3FSR = Full-Scale Range.
4Adjustable to zero.
5SNR excludes harmonics 2-9 of the fundamental.
6THD includes harmonics 2-9 of the fundamental.
7Aperture delay is the time from the rising edge on the Hold Command Input to the opening of the switch in the Track/Hold.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1, 2 (TA = –55؇C to +125؇C, VS = ؎15 V, VDD = +5 V, VSS = –5 V)
Parameter
Design Minimum
Typ
Unit
Description
START COMMAND
tSCS
10
tSCH
10
AUTOZERO
tAZS
10
tAZH
20
DATA VALID
tDVS
tDVH
HOLD COMMAND
tH
tD
DATA STROBE
tDS
tDSD
CALIBRATE PULSE WIDTH
20
ns
ns
ns
ns
1.5
CP3
0.5
CP3
13
CP3
7
ns
2
CP3
16.5
CP3
ns
Setup Time
Hold Time
Setup Time
Hold Time
Setup Time
Hold Time
Hold Time
Delay Time
Pulse Width
Delay
CALIBRATION STATUS
15
ms
Duration
NOTES
1Refer to Figures 17, 18 and 24.
2Design minimums are derived from worst case design analysis and/or simulation results. Typical values are based on characterization data. These specifications are
not guaranteed or tested.
3The time duration for this parameter varies in direct proportion to the width of the Clock Pulse (CP).
REV. 0
–3–
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