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AD1385

16-Bit 500 kHz Wide Temperature Range Sampling ADC

Analog Devices 

AD1385

DIGITAL INTERFACES

10 MHz Clock

The AD1385 requires a stable external clock. A 10 MHz clock

provides a sample rate of 500 kilosamples per second. Since

the ADC operates synchronously with this clock, clock phase

noise will appear as jitter in the aperture time. Lower clock

frequencies may be used, and the sample rate will be reduced

proportionately.

Standard TTL and CMOS crystal oscillator modules may be

used successfully to generate the required 10 MHz clock signal.

These oscillators often create considerable power supply tran-

sient noise. The oscillator should be bypassed with both ce-

ramic and solid tantalum capacitors using minimum lead

lengths. A 10 Ω resistor in series with the +5 V supply provides

additional isolation and low-pass filtering of transients pro-

duced by the oscillator. See Figure 16.

Figure 15. Recommended AD1385 Power Distribution. All

10 µF and 0.01 µF capacitors must have minimum lead

length and be located as close as possible to the by-

passed pins. Make all ground connections directly to the

groundplane.

If separate ground planes are used for Signal and Power

Ground, the supplies should be bypassed as follows:

Supply

Bypass to

± 5 V Analog

± 15 V (+VS1/–VS1)

± 15 V (+VS2/–VS2)

± 5 V Power

Signal Ground

Signal Ground

Power Ground

Power Ground

Care is also required when using a +5 V powered crystal oscil-

lator to provide the AD1385’s clock signal. These devices produce

considerable supply noise and proper bypassing is essential.

The oscillator should be bypassed with both ceramic and solid

tantalum capacitors using minimum lead lengths. A 10 Ω resis-

tor in series with the +5 V supply provides additional isolation

and low pass filtering of transients produced by the oscillator.

Reference

The AD1385 has an excellent internal reference with a typical

temperature coefficient of 5 ppm/°C. The Reference Out (Pin

39) is normally connected to Reference In (Pin 32). An exter-

nal reference may be connected to the reference input if desired.

The reference input pin requires negligible current. The refer-

ence input voltage should not exceed +11 V and must remain

more positive than 0 V. The reference output requires no by-

passing and should not be capacitively loaded. If an external

reference is used, it must have low noise to avoid degrading the

signal to noise ratio of the AD1385.

The reference output can source up to 2 mA of static (dc) cur-

rent without affecting the performance of the AD1385. By using

the AD1385’s internal reference as the system reference, gain

error over temperature can be minimized.

Figure 16. Isolating Clock Noise. Bypass Capacitors

Should Be Located Close to the Oscillator

Transmission line effects cannot be ignored when supplying the

AD1385’s 10 MHz clock. The large impedance mismatch be-

tween typical PCB traces and the AD1385’s CMOS clock input

can give rise to reflections and high frequency transients when

the 10 MHz clock source is located more than a few inches

from the AD1385. This noise can corrupt local ground and

cause degradation in the AD1385’s apparent SNR perfor-

mance. A series termination resistor of 50 Ω to 100 Ω, located

at the clock source, will usually eliminate this problem.

START CONVERT (PIN 18)

Synchronous Operation

The Start Convert signal acts like the data input of a flip-flop. A

conversion begins on the first rising clock edge after Start Con-

vert goes high (provided setup time requirements are met). This

edge drives Hold Command Out high, switching the T/H into

Hold mode. Hold Command Out (Pin 19) should be connected

to Hold Command In (Pin 22) for synchronous operation.

Continuous conversions at a 500 kHz rate may be obtained by

holding Start Convert high. The 10 MHz clock may be divided

down and used to drive the Start Convert input when a lower

conversion rate is desired. This will provide clock-synchronized

conversions at the lower rate. Synchronous conversion timing is

shown in Figures 17 and 18.

Start Convert may also be used as a gate to capture data in a

time window. The rising and falling edges of Start Convert

define the beginning and end of the window during which

conversions are desired.

Some restrictions apply when using a pulse to drive the Start

Convert input. Start Convert is ignored during a conversion for

seven clock periods after Hold Command Out goes low to sig-

nal the end of a conversion. The state of Start Convert is sampled

on each rising clock edge, beginning with the seventh edge after

Hold Command Out goes low, until a logical high is detected.

REV. 0

–9–

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