AD1876 데이터 시트보기 (PDF) - Analog Devices

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AD1876

16-Bit 100 kSPS Sampling ADC

Analog Devices 

AD1876

Internal dc error terms such as comparator voltage offset are

sampled, stored on internal capacitors and used to correct for

their corresponding errors when needed. Because these voltages

are stored on capacitors, they are subject to leakage decay and

so require refreshing. For this reason the part is required to be

run continuously—i.e., there is a minimum tS specification. If

the part has been idle for too long (i.e., tS has expired) then a

dummy conversion cycle is required to refresh these correction

voltages.

BUSY is HIGH during a conversion and goes LOW when the

conversion is completed. The twos complement output data is

presented MSB first, with MSB data valid on the rising edge of

the second DOUT CLK pulse. Subsequent data is valid on rising

edges of subsequent DOUT CLK pulses. Table I illustrates the

AD1876 output coding.

Table I. Serial Output Coding Format (Twos Complement)

VIN

–Full Scale

–Full Scale + 1 LSB

Midscale – 1 LSB

Midscale

Midscale + 1 LSB

Full Scale – 1 LSB

Full Scale

Output Code

100 . . . 00

100 . . . 01

111 . . . 11

000 . . . 00

000 . . . 01

011 . . . 10

011 . . . 11

A simple method for generating the required signals for the

AD1876 is to connect one or more AD1876s to an NPC

SM5805 digital filter. This device supplies all signals required to

operate the AD1876 at a 96 kHz sample rate, which is 2 × FS for

audio applications. This is more fully discussed in the applications

section of this data sheet, accompanied by Figures 9 and 10.

APPLICATIONS

POWER SUPPLIES AND DECOUPLING

The AD1876 has three power supply input pins. VEE and VCC

provide the supply voltages to operate the analog portions of the

AD1876 including the ADC and SHA. VDD provides the supply

voltage which operates the digital portions of the AD1876 in-

cluding the serial output port and the autocalibration controller.

5V

13 VDD

0.1µF

AD1876

VREF 11

VIN 10

AGND SENSE 9

DGND

4

AGND

8

VCC VEE

5

12

C1

SYSTEM

DIGITAL

COMMON

SYSTEM

ANALOG

COMMON

C1 12V –12V

Figure 3. Grounding and Decoupling the AD1876

Decoupling capacitors should he used on all power supply pins.

These capacitors should be placed as close as possible to the

package pins as well as the ground connections. The logic sup-

ply (VDD) should be decoupled to digital common (DGND)

with a 0.1 µF ceramic capacitor, and the analog supplies (VEE

and VCC) should be decoupled to analog common (AGND)

with 4.7 µF and 0.1 µF tantalum capacitors in parallel, repre-

sented by C1. An effort should be made to minimize the trace

length between the capacitor leads and the respective converter

power supply and common pins. The recommended decoupling

scheme is illustrated in Figure 3.

As with most high performance linear circuits, changes in the

power supplies can produce undesired changes in the perfor-

mance of the circuit. Analog Devices recommends that well

regulated power supplies with less than 1% ripple be incorpo-

rated into the design of any system using these devices.

BOARD LAYOUT

Designing with high resolution data converters requires careful

attention to board layout. Trace impedance is a significant issue.

A 1.22 mA current through a 0.5 Ω trace will develop a voltage

drop of 0.6 mV, which is 4 LSBs at the 16 bit level for a 10 V

full-scale span. In addition to ground drops, inductive and ca-

pacitive coupling need to be considered, especially when high

accuracy analog signals share the same board with digital sig-

nals. Finally, power supplies need to be decoupled in order to

filter ac noise.

Analog and digital signals should not share a common return

path. Each signal should have an appropriate analog or digital

return routed close to it. Using this approach, signal loops en-

close a small area, minimizing the inductive coupling of noise.

Wide PC tracks, large gauge wire, and ground planes are highly

recommended to provide low impedance signal paths. Separate

analog and digital ground planes are also desirable, with a single

interconnection point to minimize ground loops. Analog signals

should be routed as far as possible from digital signals and

should cross them, if at all, only at right angles. A solid analog

ground plane around the AD1876 will isolate large switching

ground currents. For these reasons, the use of wire wrap circuit

construction is not recommended; careful printed circuit con-

struction is preferred.

GROUNDING

The AD1876 has three grounding pins, designated ANALOG

GROUND (AGND), DIGITAL GROUND (DGND) and

ANALOG GROUND SENSE (AGND SENSE). The analog

ground pin is the “high quality” ground reference point for the

device. The analog ground pin should be connected to the ana-

log common point in the system.

AGND SENSE is intended to be connected to the input signal

ground reference point. This allows for slight differences in level

between the analog ground point in the system and the input

signal ground point. However, no more than 100 mV is recom-

mended between the analog ground pin and the analog ground

sense pin for specified performance.

The digital ground pin is the reference point for all of the digital

signals that operate the AD1876. This pin should be connected

to the digital common point in the system. As illustrated in Fig-

ure 3, the analog and digital grounds should be connected to-

gether at one point in the system.

REV. A

–7–

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