AD1953YSTZRL(RevA) 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD1953YSTZRL Datasheet PDF : 34 Pages
| |||
DIGITAL TIMING
Parameter
tDMD
tDMD
tDMD
tDBH
tDBH
tDBD
tDLS
tDLH
tDLD
tDDS
tDDH
tDDD
tTFS
tTBS
tTOS
tCCL
tCCH
tCLS
tCLH
tCLD
tCDS
tCDH
tCOD
tCOH
tDCD
tDCH
tPDRP
MCLK Recommended Duty Cycle @ 12.288 MHz (256 fS Mode)
MCLK Recommended Duty Cycle @ 24.576 MHz (512 fS Mode)
MCLK Delay (All Mode)
BCLK Low Pulsewidth
BCLK High Pulsewidth
BCLK Delay (to BCLKO)
LRCLK Setup
LRCLK Hold
LRCLK Delay (to LRCLKO)
SDATA Setup
SDATA Hold
SDATA Delay (to SDATAO)
TDMFS Delay (from MCLK)
TDMBC Delay (from MCLK)
TDMO Delay (from TDMBC)
CCLK Low Pulsewidth
CCLK High Pulsewidth
CLATCH Setup
CLATCH Hold
CLATCH High Pulsewidth
CDATA Setup
CDATA Hold
COUT Delay
COUT Hold
DCSOUT Delay
DCSOUT Hold
PD/RST Low Pulsewidth
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS at 44.1 kHz
Parameter
Pass-Band Ripple
Stop-Band Attenuation
Pass Band
Stop Band
Group Delay
Specifications subject to change without notice.
AD1953
Min
Typ
Max
Unit
45
55
%
40
60
%
25
ns
10
ns
10
ns
25
ns
0
ns
10
ns
25
ns
0
ns
10
ns
25
ns
35
ns
35
ns
5
ns
12
ns
12
ns
10
ns
10
ns
10
ns
0
ns
10
ns
35
ns
2
ns
35
ns
2
ns
5
ns
Min
Typ
Max
Unit
± 0.01
dB
70
dB
20
kHz
0.4535 ϫ fS
24
kHz
0.5442 ϫ fS
24.625/fS
sec
REV. A
–5–
Share Link: 