AD5171(RevPrC) 데이터 시트보기 (PDF) - Analog Devices
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AD5171 Datasheet PDF : 20 Pages
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AD5171
Preliminary Technical Data
Parameter
DYNAMIC CHARACTERISTICS 6, 10, 11
Bandwidth –3 dB
Total Harmonic Distortion
Adjustment Settling Time
OTP Settling Time12
Power-up Settling Time—Post Fuses Blown
Resistor Noise Voltage
INTERFACE TIMING CHARACTERISTICS
(Applies to all parts6,12)
SCL Clock Frequency
tBUF Bus Free Time between Start and Stop
tHD;STA Hold Time (Repeated Start)
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Start Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL signals
tSU;STO Setup Time for Stop Condition
Symbol
BW_5k
BW_10k
BW_50k
BW_100k
THD
tS1
tS_OTP
tS2
eN_WB
Conditions
Min Typ1 Max
RAB = 5 kΩ, Code = 0x20
RAB = 10 kΩ, Code = 0x20
RAB = 50 kΩ, Code = 0x20
RAB = 100 kΩ, Code = 0x20
VA =1 V rms, RAB = 10 kΩ,
VB = 0 V DC, f = 1 kHz
VA= 5 V ± 1 LSB error band,
VB = 0, measured at VW
VA = 5 V ± 1 LSB error band,
VB = 0, measured at VW
VA = 5 V ±1 LSB error band,
VB = 0, measured at VW
RAB = 5 kΩ, f = 1 kHz,
Code = 0x20
RAB = 10 kΩ, f = 1 kHz,
Code = 0x20
1500
600
110
60
0.05
5
400
5
8
12
Unit
kHz
kHz
kHz
kHz
%
µs
ms
µs
nV/√Hz
nV/√Hz
fSCL
t1
1.3
t2
After this period, the first
0.6
clock pulse is generated
t3
1.3
t4
0.6
t5
0.6
t6
t7
0.1
t8
t9
t10
0.6
400
kHz
µs
µs
µs
50
µs
µs
0.9
µs
µs
0.3
µs
0.3
µs
µs
1Typicals represent average readings at 25°C and VDD = 5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3VAB = VDD, Wiper (VW) = No connect.
4INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
5Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6Guaranteed by design and not subject to production test.
7Different from operating power supply, power supply for OTP is used one-time only.
8Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only.
9PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value result in the minimum overall power consumption.
11All dynamic characteristics use VDD = 5 V.
12Different from settling time after fuse is blown. The OTP settling time occurs once only.
t8
t9
t6
SCL
t2
t3
t4
t5
t9
t7
t8
SDA
t1
P
S
Figure 3. Interface Timing Diagram
t10
P
Rev. PrC | Page 4 of 20
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