AD5207 데이터 시트보기 (PDF) - Analog Devices
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AD5207 Datasheet PDF : 16 Pages
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AD5207
Parameter
Symbol
Conditions
Min Typ1 Max Unit
INTERFACE TIMING
CHARACTERISTICS
Applies to All Parts6, 11
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay12
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
tCH, tCL
tDS
tDH
tPD
tCSS
tCSW
tCSH0
tCSH1
tCS1
Clock Level High or Low
RL = 1 kΩ to 5 V, CL < 20 pF
10
ns
5
ns
5
ns
1
25
ns
10
ns
10
ns
0
ns
0
ns
10
ns
NOTES
1 Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = 5 V,
VSS = 0 V.
3 VAB = VDD, Wiper (VW) = No connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the AX terminals. All AX terminals are open-circuited in shut-down mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V, VSS = 0 V.
10Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
11See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of
1.5 V. Switching characteristics are measured using VDD = 5 V.
12 Propagation delay depends on value of VDD, RL, and CL; see applications text.
The AD5207 contains 474 transistors. Die Size: 67 mil × 69 mil, 4623 sq. mil.
Specifications subject to change without notice.
REV. 0
1
SDI
0
1
CLK
0
1
CS
0
VOUT
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
Figure 1a. Timing Diagram
SDI 1
(DATA IN) 0
SDO 1
(DATA OUT) 0
1
CLK
0
1
CS
0
VDD
VOUT
0V
Ax OR Dx
A'x OR D'x
Ax OR Dx
tDS
tDH
A'x OR D'x
tCH
tCSH0
tCL
tCSS
tPD_MAX
tCS1
tCSH1
tCSW
tS
؎1LSB ERROR BAND
؎1LSB
Figure 1b. Detail Timing Diagram
–3–
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