AD5255(Rev0) 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

AD5255
(Rev.:Rev0)

3-Channel Digital Potentiometer with Nonvolatile Memory

Analog Devices 

AD5255

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A0_EE 1

24 A1_EE

A1_RDAC 2

23 TEST0 (NC)

A0_RDAC 3

22 TEST1 (NC)

RS 4

WP 5

SCL 6

SDA 7

AD5255

TOP VIEW

(Not to Scale)

21 TEST2 (NC)

20 TEST3 (NC)

19 CDD, AVDD

18 A0

DGND 8

17 W0

VSS, AVSS 9

A2 10

16 B0

15 B1

W2 11

14 W1

B2 12

13 A1

NC = NO CONNECT

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

A1_EE

I2C Device Address 1 for EEMEM.

2

A1_RDAC

I2C Device Address 1 for RDAC.

3

A0_RDAC

I2C Device Address 0 for RDAC.

4

RS

Resets the scratchpad register with current contents of the EEMEM register. Factory defaults to midscale before

any programming.

5

WP

Write Protect. When active low, WP prevents any changes to the present register contents, except that RESET

and Commands 1 and 8 still refresh the RDAC register from EEMEM.

6

SCL

Serial Input Register Clock. Shifts in one bit at a time on the positive clock edges.

7

SDA

Serial Data Input. Shifts in one bit at a time on the positive clock edges. The MSB is loaded first.

8

DGND

Ground. Logic ground reference.

9

VSS

Negative Supply. Connect to 0 V for single-supply applications.

10

A2

A terminal of RDAC2.

11

W2

Wiper terminal of RDAC2.

12

B2

B terminal of RDAC2.

13

A1

A terminal of RDAC1.

14

W1

Wiper terminal of RDAC1.

15

B1

B terminal of RDAC1.

16

B0

B terminal of RDAC0.

17

W0

Wiper terminal of RDAC0.

18

A0

A terminal of RDAC0.

19

VDD

Positive Power Supply.

20

TEST3

Test Pin 3. Do not connect.

21

TEST2

Test Pin 2. Do not connect.

22

TEST1

Test Pin 1. Do not connect.

23

TEST0

Test Pin 0. Do not connect.

24

A0_EE

I2C Device Address 0 for EEMEM.

Rev. 0 | Page 7 of 20

Share Link: