AD5300CHIPS 데이터 시트보기 (PDF) - Analog Devices

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AD5300CHIPS

2.7 V to 5.5 V, 140
A, Rail-to-Rail Output 8-Bit DAC in a SOT-23

Analog Devices 

AD5300

SCLK

SYNC

DIN

DB15

DB0

DB15

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 16TH FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 16TH FALLING EDGE

Figure 23. SYNC Interrupt Facility

SYNC Interrupt

In a normal write sequence, the SYNC line is kept low for at

least 16 falling edges of SCLK and the DAC is updated on the

16th falling edge. However, if SYNC is brought high before the

16th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

invalid; neither an update of the DAC register contents or a

change in the operating mode occurs—see Figure 23.

Power-On Reset

The AD5300 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

zeros and the output voltage is 0 V. It remains there until

a valid write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the out-

put of the DAC while it is in the process of powering up.

Power-Down Modes

The AD5300 contains four separate modes of operation. These

modes are software programmable by setting two bits (DB13

and DB12) in the control register. Table I shows how the state

of the bits corresponds to the mode of operation of the device.

Table I. Modes of Operation for the AD5300

DB13

0

0

1

1

DB12

0

1

0

1

Operating Mode

Normal Operation

Power-Down Modes

1 kΩ to GND

100 kΩ to GND

Three-State

When both bits are set to 0, the part works normally with its

normal power consumption of 140 µA at 5 V. However, for the

three power-down modes, the supply current falls to 200 nA at

5 V (50 nA at 3 V). Not only does the supply current fall but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has an

advantage: the output impedance of the part is known while the

part is in power-down mode. There are three different options.

The output is connected internally to GND through a 1 kΩ resis-

tor or a 100 kΩ resistor, or it is left open-circuited (three-stated).

The output stage is illustrated in Figure 24.

RESISTOR

STRING DAC

AMPLIFIER

VOUT

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

Figure 24. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

other associated linear circuitry are all shut down when the

power-down mode is activated. However, the contents of the

DAC register are unaffected when in power-down. The time to

exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs for

VDD = 3 V (see Figure 18).

MICROPROCESSOR INTERFACING

AD5300 to ADSP-2101/ADSP-2103 Interface

Figure 25 shows a serial interface between the AD5300 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in the SPORT transmit alternate framing

mode. The ADSP-2101/ADSP-2103 SPORT is programmed

through the SPORT control register and should be configured

as follows: internal clock operation, active low framing, 16-bit

word length. Transmission is initiated by writing a word to the

Tx register after the SPORT has been enabled.

ADSP-2101/

ADSP-2103*

TFS

DT

SCLK

AD5300*

SYNC

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 25. AD5300 to ADSP-2101/ADSP-2103 Interface

REV. C

–9–

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