AD5623R-5(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD5623R-5 Datasheet PDF : 28 Pages
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AD5623R/AD5643R/AD5663R
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Limit at TMIN, TMAX
VDD = 2.7 V to 5.5 V
20
9
9
13
5
5
0
15
13
0
10
15
5
0
300
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
TIMING DIAGRAM
SCLK
SYNC
DIN
LDAC1
t10
t8
t4
DB23
t6
t5
LDAC2
CLR
t13
VOUT
t15
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t1
t3
t2
t9
t7
DB0
t14
t11
t12
Figure 2. Serial Write Operation
Rev. A | Page 7 of 28
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