AD565 데이터 시트보기 (PDF) - Analog Devices
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AD565 Datasheet PDF : 3 Pages
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MODEL
AD565S
MIN TYP
MAX
AD56ST
MIN
TYP
MAX
UNITS
DATA INPUTS (Pins 13 to 24)
TIL or 5 Volt CMOS (Tmin to Tmax)
Input Voltage
Bit ON Logic "I"
+2.0
+5.5
+2.0
+5.5
V
Bit OFF Logic "0"
+0.8
+0.8
V
Logic Current (each bit)
Bit ON Logic "I"
Bit OFF Logic "0"
+120
+35
+300
+100
+120
+300
1J.A
+35
+100
1J.A
RESOLUTION
12
12
Bits
OUTPUT
Current
Unipolar (all bits on)
-1.6
-2.0
-2.4
-1.6
-2.0
-2.4
mA
Bipolar.(all bits on or off)
:to.8
:t1.0
:t1.2
:to.8
:t1.0
:t1.2
mA
OBSOLETE Resistance (exclusive of span
resistors)
6k
Offset
Unipolar
Bipolar (Figure 5, R2 = SOn fixed)
Capacitance
Compliance Voltage
T mill to T max
-1.5
ACCURACY (error relative to
full scale) +25° C
Tmin to Tmax
8k
0.01
0.05
25
:t1/4
(0.006)
:tl/2
(0.012)
IOk
0.05
0.15
+10
:t112
(0.012)
:t3/4
(0.018)
DIFFERENTIAL
+2255"°CC
Tmin to Tmax
NONLINEARITY
:t11/2
MONOTONICITY
:t3/44
GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
I
2
5
10
IS
30
6k
8k
10k
0.01
0.05
0.05
0.1
25
-1.5
+10
:!:1/8
(0.003)
:!:1/4
(0.006)
:t1/4
(0.006)
:t112
(0.012)
:tl1/4/4
:t11l122
MONOTONICITY GUARANTEED
I
2
5
10
10
15
n
% of F.S.
% of F .S.
pF
V
LSB
% of F.S.
LSB
% of F.S.
LSB
ppm/C
ppm/oC
ppm/C
Differential Nonlinearity
2
2
ppm/C
SETTLING TIME TO 1/2LSB
All Bits ON-to-0FF or OFF-to-0N
200
400
200
400
ns
FULL SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
IS
30
30
50
IS
30
ns
30
50
ns
TEMPERATURE RANGE
Operating
-55
Storage (D Package)
-65
+125
-55
+150
-65
+125
°c
+150
°c
POWER REQUIREMENTS
Vcc, +13.5 to +16.5V de
V.-E..E-,---.1-3.5 .t.o--.---1-6.5nV__-de-
POWER SUPPLY GAIN SENSITIVITY
Vcc = +15V, :t1O%
VEE = -15V, :t1O%
PROGRAMMABLE OUTPUT
RANGE (see Figures 4.5,6)
3
5
-12
-18
3
10
15
25
0 to +5
-2.5 to +2.5
Oto+l0
-5 to +5
-10 to +10
3
5
-12
-18
3
10
15
25
0 to +5
-2.5 to +2.5
Oto+l0
-5 to +5
-10 to +10
.----
---
mA
mA
ppm of F.S.I%
ppm of F.S.I%
V
V
V
V
V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed SOn
Resistor for R2 (Fig. 4)
Bip'olar Zero Error with Fixed
Son Resistor for R 1 (Fig. 5)
Gain Adjustment Range (Fig. 4)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
REFERENCE OUTPUT
Voltage
Current (available for external
--'-lo- ads)
---
POWER DISSIPATION
Specifications
subject to change without
:to.25
:to. 15
15k
9.90
1.5
notice.
:to. I
:to.05
20k
10.00
2.5
225
:to.25
:to.15
25k
10.10
345
:to.25
I
:to. 15
15k
I
I
9.90
1.5
.
...
:to. I
:to.05
20k
10.00
2.5
225
:to.25
:to. 1
25k
10.10
I
'
--i-
345
% of F .5.
% of F.S.
% of F .5.
% of F.S.
Q
._---
V
mA
mW
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