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AD573KP

10-Bit A/D Converter

Analog Devices 

AD573

It is also possible to write a faster-executing assembly-language

routine to control the AD573. Such a routine will require a de-

lay between starting and reading the converter. This can be eas-

ily implemented by calling the Apple’s WAIT subroutine (which

resides at location $FCA8) after loading the accumulator with a

number greater than or equal to two.

8085-Series Microprocessor Interface

The AD573 can also be used with 8085-series microprocessors.

These processors use separate control signals for RD and WR,

as opposed to the single R/W control signal used in the 6800/

6500 series processors.

There are two constraints related to operation of the AD573

with 8085-series processors. The first problem is the width of

the CONVERT pulse. The circuit shown in Figure 17 (essen-

tially the same as that shown in Figure 13) will produce a wide

enough CONVERT pulse when the 8085 is running at 5 MHz.

For 8085 systems running at slower clock rates (3 MHz), the

flip-flop-based circuit can be eliminated since the WR pulse will

be approximately 500 ns wide.

The other consideration is the access time of the AD573’s three-

state output data buffers, which is 250 ns maximum. It may be

necessary to insert wait states during RD operations from the

AD573. This will not be a problem in systems using memories

with comparable access times, since wait states will have already

been provided in the basic system design.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Pin Ceramic DIP Package (“D”)

20-Pin Plastic DIP Package (“N”)

P-20A PLCC

Figure 17. AD573–8085A Interface Connections

The following assembly-language subroutine can be used to

control an AD573 residing at memory locations 3000H and

3001H. The 10 bits of data are returned (left-justified) in the

DE register pair.

ADC: LXI H, 3000 ; LOAD HL WITH AD573 ADDRESS

MOV M, A ; START CONVERSION

MVI B, 06 ; LOAD DELAY PERIOD

LOOP: DCR B

; DELAY LOOP

JNZ LOOP ;

MOV A, M ; READ LOW BYTE

ANI C0

; MASK LOWER 6 BITS

MOV E, A ; STORE CLEAN LOW BYTE IN E

INR L

; LOAD HIGH BYTE ADDRESS

MOV D, M ; MOVE HIGH BYTE TO D

RET

; EXIT

–8–

REV. A

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