AD5932YRUZ-REEL7(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD5932YRUZ-REEL7 Datasheet PDF : 28 Pages
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AD5932
TIMING SPECIFICATIONS
All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and are timed from a voltage level of (VIL + VIH)/2 (see Figure 3 to
Figure 6). DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
Limit at TMIN, TMAX
20
8
8
25
10
10
5
10
5
3
2 × t1
0
10 × t1
8 × t1
1 × t1
2 × t1
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
ns max
Conditions/Comments
MCLK period
MCLK high duration
MCLK low duration
SCLK period
SCLK high time
SCLK low time
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
Minimum CTRL pulse width
CTRL rising edge to MCLK falling edge setup time
CTRL rising edge to VOUT delay (initial pulse, includes initialization)
CTRL rising edge to VOUT delay (initial pulse, includes initialization)
Frequency change to SYNC output, each frequency increment
Frequency change to SYNC output, end of scan
MCLK falling edge to MSBOUT
1 Guaranteed by design, not production tested.
MASTER CLOCK AND TIMING DIAGRAMS
t1
MCLK
t2
t3
Figure 3. Master Clock
SCLK
FSYNC
SDATA
t5
t4
t7
t6
t8
D15
D14
t10
t9
D2
D1
D0
Figure 4. Serial Timing
D15
D14
Rev. 0 | Page 6 of 28
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