AD6634PCB 데이터 시트보기 (PDF) - Analog Devices
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AD6634PCB Datasheet PDF : 52 Pages
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AD6634
MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2
Parameter (Conditions)
Test
Temp Level Min
AD6634BBC
Typ
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM WRITE TIMING
tSC
Control3 to ↑CLK Setup Time
tHC
tHWR
tSAM
tHAM
tDRDY
tACC
Control3 to ↑CLK Hold Time
WR(RW) to RDY(DTACK) Hold Time
Address/Data to WR(RW) Setup Time
Address/Data to RDY(DTACK) Hold Time
WR(RW) to RDY(DTACK) Delay
WR(RW) to RDY(DTACK) High Delay
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
MODE INM READ TIMING
tSC
Control3 to ↑CLK Setup Time
tHC
Control3 to ↑CLK Hold Time
tSAM
Address to RD(DS) Setup Time
tHAM
tDRDY
tACC
Address to Data Hold Time
RD(DS) to RDY(DTACK) Delay
RD(DS) to RDY(DTACK) High Delay
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
2.0
2.5
7.0
3.0
5.0
8.0
4 × tCLK
5 × tCLK
5.0
2.0
0.0
5.0
8.0
8 × tCLK
10 × tCLK
MODE MNM WRITE TIMING
tSC
tHC
tHDS
tHRW
tSAM
tHAM
tDDTACK
tACC
Control3 to ↑CLK Setup Time
Control3 to ↑CLK Hold Time
DS(RD) to DTACK(RDY) Hold Time
RW(WR) to DTACK(RDY) Hold Time
Address/Data to RW(WR) Setup Time
Address/Data to RW(WR) Hold Time
DS(RD) to DTACK(RDY) Delay
RW(WR) to DTACK(RDY) Low Delay
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
2.0
2.5
8.0
7.0
3.0
5.0
8.0
4 × tCLK
MODE MNM READ TIMING
tSC
Control3 to ↑CLK Setup Time
tHC
Control3 to ↑CLK Hold Time
tHDS
DS(RD) to DTACK(RDY) Hold Time
tSAM
Address to DS(RD) Setup Time
tHAM
tDDTACK
tACC
Address to Data Hold Time
DS(RD) to DTACK(RDY) Delay
DS(RD) to DTACK(RDY) Low Delay
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
5.0
2.0
8.0
0.0
5.0
8.0
8 × tCLK
NOTES
1All Timing Specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
2CLOAD = 40 pF on all outputs, unless otherwise specified.
3Specification pertains to control signals: R/W, (WR), DS (RD), CS.
Specifications subject to change without notice.
5 × tCLK
10 × tCLK
Max
9 × tCLK
13 × tCLK
9 × tCLK
13 × tCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
–9–
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