AD6635 데이터 시트보기 (PDF) - Analog Devices
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AD6635 Datasheet PDF : 60 Pages
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AD6635
SPECIFICATIONS (continued)
GENERAL TIMING CHARACTERISTICS1, 2
Parameter (Conditions)
Temp
CLKn TIMING REQUIREMENTS
tCLK
CLKn Period
Full
tCLKL
CLKn Width Low
Full
tCLKH
CLKn Width High
Full
RESET TIMING REQUIREMENTS
tRESL
RESET Width Low
Full
INPUT WIDEBAND DATA TIMING REQUIREMENTS
tSI
Input to ≠CLKn Setup Time
Full
tHI
Input to ≠CLKn Hold Time
Full
LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS
tDLI
≠CLKn to LIx-y Output Delay Time
Full
SYNC TIMING REQUIREMENTS
tSS
SYNC(A, B, C, D) to ≠CLKn Setup Time
Full
tHS
SYNC(A, B, C, D) to ≠CLKn Hold Time
Full
SERIAL PORT CONTROL TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS2
tSCLK
SCLKn (n = 0, 4) Period
Full
tSCLKL
SCLKn Low Time
Full
tSCLKH
SCLKn High Time
Full
INPUT CHARACTERISTICS
tSSI
SDIn to ØSCLKn Setup Time
Full
tHSI
SDIn to ØSCLKn Hold Time
Full
PARALLEL PORT TIMING REQUIREMENTS
(MASTER MODE) SWITCHING CHARACTERISTICS3
tDPOCLKL
tDPOCLKLL
tDPREQ
tDPP
ØCLKn to ≠PCLKn Delay (Divide by 1)
Full
ØCLKn to ≠PCLKn Delay (Divide by 2, 4, or 8) Full
≠CLKn to ≠PxREQ Delay
≠CLKn to Px[15:0] Delay
INPUT CHARACTERISTICS
tSPA
PxACK to ØPCLKn Setup Time
tHPA
PxACK to ØPCLKn Hold Time
PARALLEL PORT TIMING REQUIREMENTS
(SLAVE MODE) SWITCHING CHARACTERISTICS3
tPOCLK
tPOCLKL
tPOCLKH
tDPREQ
tDPP
PCLKn Period
Full
PCLKn Low Period (when PCLK Divisor = 1) Full
PCLKn High Period (when PCLK Divisor = 1) Full
≠CLKn to ≠PxREQ Delay
≠CLKn to Px[15:0] Delay
Test
Level
I
IV
IV
I
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
I
IV
IV
AD6635BB
Min
Typ
Max
12.5
5.6
5.6
0.5 ϫ tCLK
0.5 ϫ tCLK
30.0
2.0
1.0
3.3
10.0
2.0
1.0
16
3.0
3.0
1.0
1.0
6.5
10.5
8.3
14.6
1.0
0.0
7.0
–3.0
12.5
2.0
2.0
0.5 ϫ tPOCLK
0.5 ϫ tPOCLK
10.0
11.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–8–
REV. 0
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