AD6653 데이터 시트보기 (PDF) - Analog Devices
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AD6653 Datasheet PDF : 80 Pages
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AD6653
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 1.
Parameter
AD6653BCPZ-125
AD6653BCPZ-150
Temperature Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Full
ACCURACY
No Missing Codes
Full
Offset Error
Full
Gain Error
Full
MATCHING CHARACTERISTIC
Offset Error
25°C
Gain Error
25°C
TEMPERATURE DRIFT
Offset Error
Full
Gain Error
Full
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full
Load Regulation @ 1.0 mA
Full
INPUT-REFERRED NOISE
VREF = 1.0 V
25°C
ANALOG INPUT
Input Span, VREF = 1.0 V
Full
Input Capacitance1
Full
VREF INPUT RESISTANCE
Full
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
Full
DRVDD (CMOS Mode)
Full
DRVDD (LVDS Mode)
Full
Supply Current
I 2,3
AVDD
Full
IDVDD2, 3
Full
IDRVDD2 (3.3 V CMOS)
Full
IDRVDD2 (1.8 V CMOS)
Full
IDRVDD2 (1.8 V LVDS)
Full
POWER CONSUMPTION
DC Input
Full
Sine Wave Input2 (DRVDD = 1.8 V) Full
Sine Wave Input2 (DRVDD = 3.3 V) Full
Standby Power4
Full
Power-Down Power
Full
12
12
Guaranteed
±0.3
±0.6
−3.9
−2.7
−0.7
−5.2
±0.3
±0.6
±0.1
±0.7
±19
±38
±5
±18
7
0.21
2
8
6
Guaranteed
±0.2
±0.6
−3.2
−0.9
±0.2
±0.7
±0.2
±0.7
±17
±49
±5
±18
7
0.21
2
8
6
1.7
1.8
1.7
3.3
1.7
1.8
390
270
20
12
57
770
1215
1275
77
2.5
1.9
1.7
3.6
1.7
1.9
1.7
689
800
8
1.8
1.9
3.3
3.6
1.8
1.9
440
785
320
24
15
57
870
905
1395
1450
77
2.5
8
Bits
% FSR
% FSR
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
1 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 11 for the equivalent analog input structure.
2 Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately
5 pF loading on each output bit.
3 The maximum limit applies to the combination of IAVDD and IDVDD currents.
4 Standby power is measured with a dc input and with the CLK pin inactive (set to AVDD or AGND).
Rev. 0 | Page 5 of 80
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