WM8728SEDS/R 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8728SEDS/R Datasheet PDF : 28 Pages
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WM8728
MASTER CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Production Data
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Master Clock Timing Information
MCLK Master clock pulse width high
tMCLKH
MCLK Master clock pulse width low
tMCLKL
MCLK Master clock cycle time
tMCLKY
MCLK Duty cycle
TEST CONDITIONS
MIN
13
13
26
40:60
TYP
MAX
60:40
DIGITAL AUDIO INTERFACE
tBCH
tBCL
BCKIN
tBCY
UNIT
ns
ns
ns
LRCIN
DIN
tDS
tLRH
tLRSU
tDH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCKIN cycle time
tBCY
BCKIN pulse width high
tBCH
BCKIN pulse width low
tBCL
LRCIN set-up time to
BCKIN rising edge
tLRSU
LRCIN hold time from
tLRH
BCKIN rising edge
DIN set-up time to BCKIN
tDS
rising edge
DIN hold time from BCKIN
tDH
rising edge
TEST CONDITIONS
MIN
TYP
MAX
40
16
16
8
8
8
8
UNIT
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.2 April 2004
8
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